leviathanch / SITCON
Slides for the talk I have very soon
☆12Updated 6 years ago
Alternatives and similar repositories for SITCON:
Users that are interested in SITCON are comparing it to the libraries listed below
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 2 weeks ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆54Updated 5 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆39Updated 9 years ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆13Updated 5 years ago
- 1st Testwafer for LibreSilicon☆15Updated 5 years ago
- A bit-serial CPU☆18Updated 5 years ago
- v8cpu is a simple multi-cycle von Neumann architecture 8-bit CPU in under 500 lines of Verilog.☆13Updated 7 years ago
- A Verilog parser for Haskell.☆34Updated 3 years ago
- chipy hdl☆17Updated 6 years ago
- A Qt5 based free VLSI development tool☆30Updated 6 years ago
- Place & Router for Minetest☆18Updated 2 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- DyRACT Open Source Repository☆16Updated 8 years ago
- CMod-S6 SoC☆40Updated 7 years ago
- L3 based MIPS specification and emulator☆15Updated 3 years ago
- Enigma in FPGA☆29Updated 5 years ago
- Experiments with Yosys cxxrtl backend☆48Updated 2 months ago
- A 6800 CPU written in nMigen☆49Updated 3 years ago
- An executable specification of the RISCV ISA in L3.☆41Updated 6 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- A reimplementation of a tiny stack CPU☆82Updated last year
- The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github…☆31Updated last week
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆83Updated 5 years ago
- RISC-V SMBIOS Type 44 Spec☆12Updated last year
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆32Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- UTF8 Validator (C edition)☆23Updated 3 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago