Alternatives and similar repositories for SITCON

Users that are interested in SITCON are comparing it to the libraries listed below

• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆28Updated 3 weeks ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago
• warclab / dyract
  DyRACT Open Source Repository
  ☆16Updated 9 years ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 5 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆34Updated 3 years ago
• mballance / fwrisc-s
  ☆10Updated 5 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 7 years ago
• chipforge / PearlRiver
  1st Testwafer for LibreSilicon
  ☆15Updated 6 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆55Updated 5 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• parallella / parallella-riscv
  RISC-V port to Parallella Board
  ☆12Updated 8 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 4 months ago
• olofk / simple_spi
  SPI core
  ☆15Updated 5 years ago
• ujamjar / hardcaml-riscv
  RISC-V instruction set CPUs in HardCaml
  ☆15Updated 8 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• acjf3 / l3mips
  L3 based MIPS specification and emulator
  ☆15Updated 3 years ago
• adamwalker / fpga-kvs
  A networked FPGA key-value store written in Clash
  ☆28Updated last year
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• betrusted-io / betrusted-ec
  Betrusted embedded controller (UP5K)
  ☆45Updated last year
• mmicko / enigmaFPGA
  Enigma in FPGA
  ☆29Updated 6 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• leviathanch / libresiliconprocess
  ☆29Updated 5 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆34Updated 3 years ago
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 4 years ago
• vsergeev / v8cpu
  v8cpu is a simple multi-cycle von Neumann architecture 8-bit CPU in under 500 lines of Verilog.
  ☆13Updated 7 years ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆21Updated 8 years ago
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆45Updated 6 months ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆40Updated 2 years ago