leviathanch / SITCON

Related projects ⓘ

Alternatives and complementary repositories for SITCON

• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated 2 weeks ago
• chipforge / PearlRiver
  1st Testwafer for LibreSilicon
  ☆15Updated 5 years ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆18Updated 5 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆54Updated 5 years ago
• ZipCPU / zipversa
  A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
  ☆13Updated 5 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 6 years ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 8 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆37Updated 8 years ago
• swetland / gateware
  A collection of little open source FPGA hobby projects
  ☆46Updated 4 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 5 years ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆21Updated 7 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆33Updated 3 years ago
• Lichtso / UnikernelExperiments
  TCP/IPv6-enabled Pine64+ bootloader
  ☆13Updated 7 years ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆30Updated 10 months ago
• mmicko / enigmaFPGA
  Enigma in FPGA
  ☆26Updated 5 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆47Updated 10 months ago
• ArcaneNibble / yavhdl
  Yet Another VHDL tool
  ☆31Updated 7 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• google / minetest_pnr
  Place & Router for Minetest
  ☆18Updated 2 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆34Updated 8 months ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆41Updated 5 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 2 years ago
• ucb-bar / fpga-spartan6
  Support for zScale on Spartan6 FPGAs
  ☆15Updated 9 years ago
• dominiksalvet / risc63
  Custom 64-bit pipelined RISC processor
  ☆13Updated 4 months ago
• libresilicon / coriolis
  autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
  ☆15Updated 6 years ago
• f4pga / ideas
  Random ideas and interesting ideas for things we hope to eventually do.
  ☆86Updated 2 years ago
• leviathanch / libresiliconprocess
  ☆29Updated 5 years ago
• embecosm / chiphack
  Repository and Wiki for Chip Hack events.
  ☆50Updated 3 years ago
• betrusted-io / betrusted-ec
  Betrusted embedded controller (UP5K)
  ☆45Updated 10 months ago