Poofjunior / fpga_fast_serial_sortLinks
a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
☆41Updated 9 years ago
Alternatives and similar repositories for fpga_fast_serial_sort
Users that are interested in fpga_fast_serial_sort are comparing it to the libraries listed below
Sorting:
- An Open Source configuration of the Arty platform☆132Updated last year
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆123Updated 9 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆68Updated 2 months ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated last year
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆44Updated 3 years ago
- ☆63Updated 6 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- OpenFPGA☆34Updated 7 years ago
- Demo SoC for SiliconCompiler.☆62Updated 3 weeks ago
- Open Processor Architecture☆26Updated 9 years ago
- A 32-bit RISC-V processor for mriscv project☆59Updated 8 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆111Updated 2 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated last month
- SymbiFlow WIP changes for Yosys Open SYnthesis Suite☆39Updated last year
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆156Updated 7 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆89Updated 6 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- mirror of https://git.elphel.com/Elphel/x393☆40Updated 2 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆18Updated last year
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- DyRACT Open Source Repository☆16Updated 9 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago