Poofjunior / fpga_fast_serial_sortLinks
a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
☆41Updated 10 years ago
Alternatives and similar repositories for fpga_fast_serial_sort
Users that are interested in fpga_fast_serial_sort are comparing it to the libraries listed below
Sorting:
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Updated 6 years ago
- OpenFPGA☆34Updated 7 years ago
- DyRACT Open Source Repository☆16Updated 9 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- Open Processor Architecture☆26Updated 9 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 3 weeks ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated last year
- ☆63Updated 7 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆112Updated 2 years ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- A 32-bit RISC-V processor for mriscv project☆60Updated 8 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- An Open Source configuration of the Arty platform☆131Updated last year
- SPI core☆14Updated 6 years ago
- ReconOS - Operating System for Reconfigurable Hardware☆29Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/x393☆40Updated 2 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- a playground for xilinx zynq fpga experiments☆49Updated 7 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆19Updated last year
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆37Updated 3 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Updated 3 years ago
- Repository and Wiki for Chip Hack events.☆52Updated 4 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- Sample minimal Vivado project for Parallella FPGA☆45Updated 9 years ago