JohnDRO / Golirev-IDE
An online Verilog IDE based on YosysJS.
☆24Updated 8 years ago
Related projects ⓘ
Alternatives and complementary repositories for Golirev-IDE
- OpenFPGA☆33Updated 6 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 2 weeks ago
- Project X-Ray Database: XC7 Series☆63Updated 2 years ago
- A bit-serial CPU☆18Updated 5 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆32Updated 2 years ago
- chipy hdl☆17Updated 6 years ago
- Open Processor Architecture☆26Updated 8 years ago
- Experiments with Yosys cxxrtl backend☆47Updated 10 months ago
- RISC-V instruction set CPUs in HardCaml☆15Updated 8 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- A Verilog Synthesis Regression Test☆34Updated 8 months ago
- Benchmarks for Yosys development☆22Updated 4 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Yosys Plugins☆20Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆60Updated 3 weeks ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 5 years ago
- A Verilog parser for Haskell.☆33Updated 3 years ago
- a simple C-to-Verilog compiler☆47Updated 7 years ago
- The BERI and CHERI processor and hardware platform☆46Updated 7 years ago
- PicoRV☆43Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Torc: Tools for Open Reconfigurable Computing☆39Updated 7 years ago
- A reimplementation of a tiny stack CPU☆80Updated 11 months ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆24Updated 4 years ago
- ☆58Updated last year
- ☆18Updated 4 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- This is a simple UART echo test for the iCEstick Evaluation Kit☆37Updated 5 years ago