Alternatives and similar repositories for Golirev-IDE

Users that are interested in Golirev-IDE are comparing it to the libraries listed below

• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 4 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• cseed / cynth
  a simple C-to-Verilog compiler
  ☆51Updated 8 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆29Updated 2 weeks ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• knielsen / ice40_viewer
  ☆61Updated last year
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆49Updated 4 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 7 months ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 5 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆36Updated 4 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆95Updated 3 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated last year
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆56Updated 5 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆37Updated 4 years ago
• aeste / aemb
  Multi-threaded 32-bit embedded core family.
  ☆24Updated 13 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 7 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆70Updated 3 years ago
• KestrelComputer / S64X7
  64-bit MISC Architecture CPU
  ☆12Updated 8 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• ArcaneNibble / project-chibi
  Altera MAX V bitstream documentation -- CLEANUP PENDING
  ☆19Updated 5 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• combinatorylogic / soc
  An experimental System-on-Chip with a custom compiler toolchain.
  ☆60Updated 5 years ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆75Updated 6 years ago
• mmicko / enigmaFPGA
  Enigma in FPGA
  ☆29Updated 6 years ago
• cambridgehackers / fpgajtag
  A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
  ☆36Updated 3 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago