antmicro / verilator-dynamic-scheduler-examples

Related projects ⓘ

Alternatives and complementary repositories for verilator-dynamic-scheduler-examples

• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 4 months ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated 2 weeks ago
• b224hisl / rioschip
  ☆33Updated last year
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆44Updated this week
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆35Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• enjoy-digital / litesata_axiom
  ☆12Updated 3 years ago
• dovebutch / tlv-comp
  ☆26Updated 3 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• bobbl / rudolv
  RISC-V processor
  ☆28Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆52Updated 2 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆19Updated 3 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• andylithia / Project-Yatsuhashi-Chip1
  ☆39Updated last year
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 6 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆60Updated 3 weeks ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆20Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆28Updated last month
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆47Updated 9 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆21Updated 4 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 4 months ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆20Updated 3 years ago