popovicu / risc-v-bare-metal-fake-kernelLinks
☆17Updated 2 years ago
Alternatives and similar repositories for risc-v-bare-metal-fake-kernel
Users that are interested in risc-v-bare-metal-fake-kernel are comparing it to the libraries listed below
Sorting:
- iCESugar-nano FPGA board (base on iCE40LP1K)☆139Updated 3 months ago
- Combined ESP32C3 and iCE40 FPGA board☆77Updated 2 months ago
- yosys, nextpnr, apicula and openFPGALoader in vscode using OSS-CAD-Suite☆38Updated last year
- ☆13Updated last year
- Run Linux on MCUs such as ESP32C3 with RISC-V emulator☆124Updated last year
- Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.☆227Updated last week
- Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…☆73Updated 3 months ago
- Linux capable RISC-V SoC designed to be readable and useful.☆154Updated last week
- Linux on a $0.15 RISC-V microcontroller☆269Updated 3 months ago
- Bare-metal programming on RP2350 dual-core ARM Cortex-m33/RISC-V Hazard3 (non-SDK)☆21Updated 7 months ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆103Updated 2 years ago
- Apache NuttX RTOS for Pine64 Star64 64-bit RISC-V SBC (StarFive JH7110)☆32Updated this week
- RISC-V Assembly Language Programming: Using ESP32-C3 and QEMU☆22Updated 3 years ago
- Example of ESP32-C3 (rev. 3 and later) "direct boot" feature.☆75Updated 2 years ago
- ☆16Updated 10 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆112Updated last year
- FLIX-V: FPGA, Linux and RISC-V☆41Updated 2 years ago
- Code for the "fake BIOS" RISC-V example☆35Updated 2 years ago
- sump3 logic analyzer☆31Updated 2 weeks ago
- Open source FreeRTOS SDK for EOS S3 MCU+eFPGA SoC including gateware, software and documentation under QuickLogic Open Reconfigurable Com…☆49Updated 2 years ago
- ☆43Updated 4 years ago
- Example projects/code for the OrangeCrab☆107Updated last year
- Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP☆40Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated this week
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆33Updated last year
- An attempt to recreate the RP2040 PIO in an FPGA☆306Updated last year
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆86Updated last week
- K210 run linux nommu (From Damien Le Moal's patch)☆159Updated 2 years ago
- My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.☆47Updated last year
- RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card☆42Updated 3 months ago