Alternatives and similar repositories for KASIRGA-GUN

Users that are interested in KASIRGA-GUN are comparing it to the libraries listed below

• TUTEL-TUBITAK / TEKNOFEST_2023_Cip_Tasarim_Yarismasi
  Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…
  ☆20Updated 2 years ago
• kirbyydoge / kasirga_gok_2023
  Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı
  ☆17Updated 2 years ago
• muhammedkocaoglu / mystic_riscv64
  64-bit RISC-V processor
  ☆16Updated 3 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆185Updated 2 weeks ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆162Updated last year
• FPGADude / Digital-Design
  Verilog HDL files
  ☆161Updated last year
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆118Updated 2 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆165Updated last year
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆143Updated 2 months ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆71Updated 3 years ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆280Updated 6 months ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆403Updated last year
• raysalemi / Python4RTLVerification
  ☆170Updated 3 years ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆14Updated 2 years ago
• martinKindall / risc-v-single-cycle
  A Single Cycle Risc-V 32 bit CPU
  ☆55Updated this week
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆147Updated 5 years ago
• karimmahmoud22 / SystemVerilog-For-Verification
  ☆39Updated last year
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆56Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆470Updated last month
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆158Updated 4 years ago
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆18Updated 2 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆114Updated 11 months ago
• Artityagi123456789 / 15DaysofUVM
  ☆23Updated last year
• Ummidichandrika / 100-Days-of-RTL
  ☆117Updated last year
• accellera-official / uvm-core
  ☆103Updated last year
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆38Updated 3 months ago
• pengwubj / hw_interview_questions
  A collection of commonly asked RTL design interview questions
  ☆37Updated 8 years ago
• Abhishekvlsi / 108-RTL-Projects
  Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…
  ☆26Updated 11 months ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆22Updated 2 years ago