Alternatives and similar repositories for KASIRGA-GUN

Users that are interested in KASIRGA-GUN are comparing it to the libraries listed below

• TUTEL-TUBITAK / TEKNOFEST_2023_Cip_Tasarim_Yarismasi
  Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…
  ☆21Updated 2 years ago
• kirbyydoge / kasirga_gok_2023
  Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı
  ☆16Updated 2 years ago
• muhammedkocaoglu / mystic_riscv64
  64-bit RISC-V processor
  ☆16Updated 2 years ago
• muhammedkocaoglu / SystemVerilog-Tutorials
  SystemVerilog derslerinde yazdığım kodları içermektedir.
  ☆14Updated last year
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆149Updated 3 weeks ago
• A-T-Kristensen / simple-alu-uvm
  This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit
  ☆24Updated 6 years ago
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆18Updated last week
• kerimturak / tcore-rv32imc
  ☆12Updated 2 months ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated last year
• Marco-Winzker / FPGA-FIR-Filter
  Lecture about FIR filter on an FPGA
  ☆12Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated last year
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆93Updated last year
• accellera-official / uvm-core
  ☆86Updated 9 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆128Updated 6 years ago
• shubhi704 / APB-Protocol
  ☆43Updated 3 years ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆61Updated 4 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆48Updated 4 years ago
• martinKindall / risc-v-single-cycle
  A Single Cycle Risc-V 32 bit CPU
  ☆46Updated 2 years ago
• sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog
  Single Cycle RISC MIPS Processor
  ☆33Updated 3 years ago
• kirbyydoge / kasirga_2023
  Kasırga Sayısal Görüntü İşleme Kategorisi Hızlandırıcı Tasarımı
  ☆12Updated 2 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆49Updated 11 months ago
• Devipriya1921 / VSDBabySoC_ICC2
  ☆10Updated 2 years ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆19Updated last year
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆25Updated 3 years ago
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆19Updated 2 years ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆34Updated 2 years ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆78Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 5 months ago