TUTEL-TUBITAK / TEKNOFEST_2023_Cip_Tasarim_Yarismasi
Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak için kullanılacaktır.
☆21Updated 2 years ago
Alternatives and similar repositories for TEKNOFEST_2023_Cip_Tasarim_Yarismasi:
Users that are interested in TEKNOFEST_2023_Cip_Tasarim_Yarismasi are comparing it to the libraries listed below
- 64-bit RISC-V processor☆16Updated 2 years ago
- Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C☆17Updated 2 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆22Updated 6 years ago
- ☆12Updated 2 weeks ago
- ☆55Updated 9 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆83Updated last year
- KASIRGA-GUN | RV32IMCX☆12Updated 8 months ago
- Lecture about FIR filter on an FPGA☆12Updated 11 months ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- ☆16Updated 9 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Basic RISC-V Test SoC☆119Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆17Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- SystemVerilog Tutorial☆138Updated 3 weeks ago
- Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)☆33Updated last week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆66Updated this week
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆44Updated 9 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 3 months ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 5 months ago
- UART design in SV and verification using UVM and SV☆43Updated 5 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆83Updated 5 years ago
- Single Cycle RISC MIPS Processor☆33Updated 3 years ago