Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak için kullanılacaktır.
☆24Apr 13, 2023Updated 3 years ago
Alternatives and similar repositories for TEKNOFEST_2023_Cip_Tasarim_Yarismasi
Users that are interested in TEKNOFEST_2023_Cip_Tasarim_Yarismasi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Advanced Verification Methodologies for RISC-V and related IP☆10Jan 16, 2023Updated 3 years ago
- Kasırga Sayısal Görüntü İşleme Kategorisi Hızlandırıcı Tasarımı☆15May 27, 2023Updated 3 years ago
- Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı☆20May 27, 2023Updated 3 years ago
- Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.☆16May 29, 2020Updated 6 years ago
- ☆18Oct 6, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆18Mar 13, 2024Updated 2 years ago
- Interactive code generators for Gowin FPGAs☆23Mar 16, 2023Updated 3 years ago
- ☆18Jan 16, 2025Updated last year
- Compiler Level RISC-V Encryption Tool https://ieeexplore.ieee.org/document/9833625☆13Jan 19, 2023Updated 3 years ago
- Teknofest 2018 Yapay Zeka yarışması için geliştirdiğim Soru-Cevap modeli.☆12Oct 3, 2025Updated last year
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆29Jul 27, 2018Updated 8 years ago
- LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framew…☆34Jul 6, 2026Updated 4 months ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆36Nov 1, 2025Updated last year
- RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione☆38Oct 30, 2026Updated last week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Feb 22, 2026Updated 8 months ago
- ☆31Updated this week
- ☆11Nov 10, 2020Updated 5 years ago
- Device: Zedboard xc7z020clg484-1, Clock Rate: 319 MHz, Tool: Vivado 2018.3, Language: Verilog☆12Feb 1, 2021Updated 5 years ago
- This repository contains a SystemVerilog implementation of a parametrized Round Robin arbiter with three instantiation options☆14Jan 28, 2024Updated 2 years ago
- A short and on point tutorial on how to use an ASIC logic synthesis tool☆17Jul 3, 2026Updated 4 months ago
- A light-weight hardware oriented synchronous stream cipher.☆13Mar 19, 2022Updated 4 years ago
- ⚡️Official Image-charts Python library☆12Updated this week
- KOUSTECH'in Savaşan IHA Yarismasi sisteminde mesajları yönlendirmek ve sistem durumunu tutmaktan sorumlu ana/yönetici servis☆15Aug 30, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- ☆12Sep 1, 2025Updated last year
- A documentation on my findings in Cadence☆11Feb 27, 2020Updated 6 years ago
- Kogge-Stone Adder in Verilog☆18Nov 19, 2021Updated 4 years ago
- Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy.…☆10Jul 22, 2020Updated 6 years ago
- KASIRGA - GUN | RV32IMCX☆10Aug 14, 2024Updated 2 years ago
- ☆21Oct 14, 2023Updated 3 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- 64-bit RISC-V processor☆18Nov 30, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A high-performance, PPA (Performance, Power, Area) optimized Arithmetic Logic Unit (ALU) designed for a 32-bit processor core. This proje…☆15Oct 21, 2026Updated 2 weeks ago
- Docker image generation for Xilinx Petalinux Tools and Vivado☆17Oct 10, 2025Updated last year
- Motion Estimation implementation by using Verilog HDL☆14Jun 17, 2024Updated 2 years ago
- VS Code extension that exposes Google Antigravity models to Copilot Chat using the official BYOK interface. Manages a local OpenAI-compat…☆18Jan 19, 2026Updated 9 months ago
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆14Mar 14, 2026Updated 7 months ago
- fbDOOM with RISC-V Vector optimizations☆18Aug 30, 2023Updated 3 years ago
- RISC-V Nox core☆73Jul 22, 2025Updated last year