Alternatives and similar repositories for mystic_riscv64

Users that are interested in mystic_riscv64 are comparing it to the libraries listed below

• muhammedkocaoglu / SystemVerilog-Tutorials
  SystemVerilog derslerinde yazdığım kodları içermektedir.
  ☆14Updated last year
• TUTEL-TUBITAK / TEKNOFEST_2023_Cip_Tasarim_Yarismasi
  Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…
  ☆20Updated 2 years ago
• mbaykenar / mpw7_yonga_soc
  Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C
  ☆18Updated 2 years ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• Marco-Winzker / FPGA-FIR-Filter
  Lecture about FIR filter on an FPGA
  ☆12Updated last year
• jiacaiyuan / i2c_slave
  I2C slave Verilog Design and TestBench
  ☆25Updated 6 years ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆144Updated 6 years ago
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆18Updated last year
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆181Updated 2 weeks ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆20Updated last year
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆39Updated last year
• kerimturak / tcore-rv32imc
  ☆13Updated 5 months ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆77Updated 2 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆77Updated 13 years ago
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆36Updated 3 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated 2 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆110Updated last year
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆88Updated 2 years ago
• jamieiles / uart
  Verilog UART
  ☆180Updated 12 years ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆157Updated last year
• raysalemi / Python4RTLVerification
  ☆166Updated 3 years ago
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆30Updated 3 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆61Updated 4 years ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆65Updated 3 years ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆39Updated 2 years ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆138Updated 2 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆172Updated 4 months ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆34Updated 2 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆58Updated 9 years ago