muhammedkocaoglu / mystic_riscv64
64-bit RISC-V processor
☆14Updated 2 years ago
Alternatives and similar repositories for mystic_riscv64:
Users that are interested in mystic_riscv64 are comparing it to the libraries listed below
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆13Updated last year
- Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…☆20Updated last year
- Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C☆16Updated 2 years ago
- ☆12Updated 2 weeks ago
- ☆14Updated last year
- ☆17Updated 2 years ago
- ☆16Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- opensource EDA tool flor VLSI design☆32Updated last year
- Single Cycle RISC MIPS Processor☆32Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆54Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆33Updated 2 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆22Updated 6 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- ☆39Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆56Updated 2 years ago
- Lecture about FIR filter on an FPGA☆11Updated 9 months ago
- ☆40Updated 3 years ago
- Static Timing Analysis Full Course☆49Updated 2 years ago
- KASIRGA-GUN | RV32IMCX☆11Updated 6 months ago
- SystemVerilog UVM testbench example☆30Updated 10 months ago
- Architectural design of data router in verilog☆30Updated 5 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆67Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆81Updated last year
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆42Updated last year
- Implementation of RISC-V RV32I☆17Updated 2 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆27Updated 6 years ago