muhammedkocaoglu / mystic_riscv64
64-bit RISC-V processor
☆12Updated last year
Related projects ⓘ
Alternatives and complementary repositories for mystic_riscv64
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆12Updated 11 months ago
- Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C☆15Updated last year
- Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…☆19Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆48Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- ☆16Updated last year
- Lecture about FIR filter on an FPGA☆13Updated 5 months ago
- RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.☆18Updated 2 years ago
- ☆14Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year
- ☆39Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆25Updated 8 months ago
- SystemVerilog Tutorial☆113Updated 11 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆52Updated last week
- Pipelined RISC-V RV32I Core in Verilog☆35Updated last year
- KASIRGA-GUN | RV32IMCX☆12Updated 2 months ago
- opensource EDA tool flor VLSI design☆29Updated last year
- Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.☆31Updated 2 years ago
- ☆36Updated 3 years ago
- Complete tutorial code.☆12Updated 6 months ago
- Two Stage CMOS Operational Amplifier IP Design using Skywater 130nm Technology☆11Updated 2 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆18Updated 6 years ago
- ☆13Updated 3 weeks ago
- ☆10Updated 3 months ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆29Updated 3 years ago
- ☆120Updated 2 years ago
- Static Timing Analysis Full Course☆43Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆28Updated 2 years ago