Alternatives and similar repositories for riscv-assembler

Users that are interested in riscv-assembler are comparing it to the libraries listed below

• leros-dev / leros
  A Tiny Processor Core
  ☆114Updated 5 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆134Updated this week
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆151Updated 6 years ago
• bsc-loca / sargantana
  ☆121Updated 4 months ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆198Updated 4 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆237Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆192Updated 2 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆252Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆130Updated 3 months ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆102Updated 8 months ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆183Updated last year
• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆189Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆79Updated last year
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆76Updated last month
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆89Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆153Updated last year
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆160Updated 4 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆175Updated this week
• chipsalliance / VeeR-ISS
  ☆150Updated 2 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 10 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆181Updated 8 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆82Updated 3 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆136Updated last month
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆233Updated last week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆195Updated this week