jmduarte / HLS_hls4ml_TutorialLinks
HLS & hls4ml Tutorial
☆10Updated 4 years ago
Alternatives and similar repositories for HLS_hls4ml_Tutorial
Users that are interested in HLS_hls4ml_Tutorial are comparing it to the libraries listed below
Sorting:
- A collection of tutorials for the fpgaConvNet framework.☆41Updated 9 months ago
- ☆14Updated 3 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- PYNQ Composabe Overlays☆73Updated last year
- ☆30Updated 7 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆81Updated last month
- Systolic array based simple TPU for CNN on PYNQ-Z2☆33Updated 3 years ago
- Live demo of hls4ml on embedded platforms such as the Pynq-Z2☆10Updated 10 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆55Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago
- A floating-point matrix multiplication implemented in hardware☆31Updated 4 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆7Updated last year
- ☆35Updated 3 months ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- eyeriss-chisel3☆40Updated 3 years ago
- Vitis HLS Library for FINN☆198Updated 3 weeks ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆15Updated last year
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆39Updated 11 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b …☆46Updated 8 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Board: PYNQ-Z2, Vitis version: 2022.1☆19Updated 9 months ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 7 months ago
- ☆22Updated 3 years ago
- ☆34Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago