Alternatives and similar repositories for HLS_hls4ml_Tutorial:

Users that are interested in HLS_hls4ml_Tutorial are comparing it to the libraries listed below

• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆76Updated 2 months ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆44Updated 11 months ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆39Updated 7 months ago
• sumilao / Zynq-7000-DPU-TRD
  Zynq-7000 DPU TRD
  ☆44Updated 5 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆30Updated 2 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆192Updated this week
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆71Updated last year
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 4 years ago
• bol-edu / course-lab_1
  Board: PYNQ-Z2, Vitis version: 2022.1
  ☆19Updated 7 months ago
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆47Updated 9 months ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆71Updated 10 months ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆14Updated 4 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆24Updated 4 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆50Updated 4 years ago
• AlexMontgomerie / fpgaconvnet-hls
  ☆29Updated 5 months ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆63Updated 6 years ago
• fastmachinelearning / hls4ml-live-demo
  Live demo of hls4ml on embedded platforms such as the Pynq-Z2
  ☆10Updated 8 months ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆86Updated 4 years ago
• louislxw / pe_array
  A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…
  ☆10Updated 10 months ago
• RakeshUIUC / multihead_attn_accelerator
  Accelerate multihead attention transformer model using HLS for FPGA
  ☆11Updated last year
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆29Updated 5 months ago
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆63Updated 3 months ago
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆51Updated 6 years ago
• sharc-lab / FPGA_ECE8893
  ☆35Updated last month
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated last year
• Xilinx / PYNQ-ZU
  PYNQ-ZU, AUP UltraScale+ MPSoC academic board
  ☆23Updated this week
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆43Updated 2 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆80Updated 2 years ago