Alternatives and similar repositories for hls4ml-live-demo

Users that are interested in hls4ml-live-demo are comparing it to the libraries listed below

• fastmachinelearning / models
  Models and examples built with hls4ml
  ☆12Updated 5 years ago
• IMPETUS-UdeS / rule4ml
  Resource Utilization and Latency Estimation for ML on FPGA.
  ☆15Updated 3 weeks ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆87Updated 2 months ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆204Updated last week
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• calad0i / HGQ
  High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs
  ☆32Updated 2 weeks ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆200Updated 3 years ago
• fastmachinelearning / hls4ml-tutorial
  Tutorial notebooks for hls4ml
  ☆354Updated last month
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆226Updated 4 months ago
• thesps / conifer
  Fast inference of Boosted Decision Trees in FPGAs
  ☆55Updated this week
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆152Updated 2 years ago
• KULeuven-MICAS / zigzag
  HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
  ☆155Updated 2 weeks ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆43Updated 10 months ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆173Updated this week
• awai54st / LUTNet
  ☆58Updated 5 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆54Updated last year
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆81Updated last year
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆222Updated 2 years ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆148Updated this week
• AlexMontgomerie / fpgaconvnet-hls
  ☆30Updated 9 months ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆224Updated last year
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆130Updated last year
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆55Updated 2 years ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆30Updated 9 months ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆128Updated 5 years ago
• manoharvhr / PYNQ-Torch
  PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform
  ☆72Updated 5 years ago