fastmachinelearning / hls4ml-live-demo
Live demo of hls4ml on embedded platforms such as the Pynq-Z2
☆10Updated 8 months ago
Alternatives and similar repositories for hls4ml-live-demo
Users that are interested in hls4ml-live-demo are comparing it to the libraries listed below
Sorting:
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆77Updated this week
- Models and examples built with hls4ml☆12Updated 5 years ago
- Model zoo for the Quantized ONNX (QONNX) model format☆12Updated 3 months ago
- ☆30Updated 6 months ago
- IPbus Builder Tool☆13Updated 3 months ago
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆30Updated last month
- Fast inference of Boosted Decision Trees in FPGAs☆54Updated last month
- ☆93Updated 11 months ago
- Resource Utilization and Latency Estimation for ML on FPGA.☆10Updated this week
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 7 months ago
- PYNQ-ZU, AUP UltraScale+ MPSoC academic board☆23Updated 3 weeks ago
- PYNQ Composabe Overlays☆71Updated 11 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆40Updated 2 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆53Updated last year
- ☆15Updated this week
- ☆57Updated 5 years ago
- Open-Source HLS Examples for Microchip FPGAs☆44Updated this week
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 5 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆32Updated last year
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 6 months ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆47Updated 9 months ago
- Vitis HLS Library for FINN☆195Updated last week
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆54Updated 3 months ago
- ☆57Updated last year
- HLS & hls4ml Tutorial☆10Updated 4 years ago
- ☆23Updated 2 years ago