fastmachinelearning / hls4ml-live-demoLinks
Live demo of hls4ml on embedded platforms such as the Pynq-Z2
☆11Updated last year
Alternatives and similar repositories for hls4ml-live-demo
Users that are interested in hls4ml-live-demo are comparing it to the libraries listed below
Sorting:
- Models and examples built with hls4ml☆12Updated 5 years ago
- Vitis HLS Library for FINN☆210Updated last week
- Train and deploy LUT-based neural networks on FPGAs☆105Updated last year
- High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs☆38Updated 4 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆100Updated last week
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- Tutorial notebooks for hls4ml☆396Updated last week
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆55Updated last year
- Dataflow QNN inference accelerator examples on FPGAs☆239Updated 3 months ago
- NeuraLUT-Assemble☆46Updated 4 months ago
- DPU on PYNQ☆234Updated 4 months ago
- A collection of tutorials for the fpgaConvNet framework.☆47Updated last year
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Updated 4 years ago
- Fast inference of Boosted Decision Trees in FPGAs☆57Updated last month
- Resource Utilization and Latency Estimation for ML on FPGA.☆17Updated 2 months ago
- ☆35Updated 6 years ago
- PYNQ Composabe Overlays☆73Updated last year
- A course based on FINN with hands on Lectures, Examples and Labs to go from 0 to a full custom Quantized Neural Network running on your v…☆42Updated 5 months ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- ☆64Updated 5 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 4 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆70Updated 5 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆72Updated 5 years ago
- Library of approximate arithmetic circuits☆61Updated 3 years ago
- FINN+ is an extended version of FINN, a dataflow compiler for QNN inference on FPGAs. It is maintained by a group of researchers at Pader…☆35Updated this week
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆46Updated last month
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆30Updated last year
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago