Alternatives and similar repositories for TrivialMIPS_Software:

Users that are interested in TrivialMIPS_Software are comparing it to the libraries listed below

• CircuitCoder / mill
  RV32I by cats
  ☆17Updated last year
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆56Updated 3 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 10 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated this week
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated last year
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆19Updated this week
• OpenXiangShan / nexus-am
  ☆33Updated this week
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 6 months ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆14Updated 7 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆12Updated 5 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated 2 months ago
• cyyself / cpu232
  The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully
  ☆9Updated 4 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆13Updated 2 months ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• jiegec / jtag-remote-server
  Remote JTAG server for remote debugging
  ☆36Updated 9 months ago
• jiegec / kb
  My knowledge base
  ☆42Updated last week
• rgwan / bapi-rv32i
  A extremely size-optimized RV32I soft processor for FPGA.
  ☆27Updated 6 years ago
• atrosinenko / memtest86-plus-riscv
  Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)
  ☆15Updated 5 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆75Updated this week
• sequencer / arithmetic
  ☆32Updated this week
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆35Updated this week
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆29Updated this week
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated 10 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated 11 months ago
• oscourse-tsinghua / cpu-testcase
  Test cases for MIPS CPU implementation
  ☆12Updated 5 years ago