zhutmost / edgeboardLinks
Make Baidu EdgeBoard Lite as a general Zynq FPGA development board
☆29Updated 2 years ago
Alternatives and similar repositories for edgeboard
Users that are interested in edgeboard are comparing it to the libraries listed below
Sorting:
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆80Updated last year
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆51Updated 2 years ago
- 国产VU13P加速卡资料☆79Updated 8 months ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆27Updated last year
- FPGA Technology Exchange Group相关文件管理☆54Updated last month
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆26Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆75Updated last year
- ☆24Updated 9 years ago
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆140Updated last year
- Interface Protocol in Verilog☆50Updated 6 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆37Updated last year
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆127Updated 3 years ago
- ☆80Updated 3 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- understanding of cocotb (In Chinese Only)☆20Updated 6 months ago
- A dual-camera based on OminiVison 5460 for GoWin GW2A-55K Combat Board☆33Updated 4 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆146Updated last year
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- Cortex M0 based SoC☆75Updated 4 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆71Updated 7 months ago
- 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例☆114Updated last year
- Implement a bitonic sorting network on FPGA☆46Updated 4 years ago
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆27Updated 2 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆77Updated 4 years ago
- CNN accelerator implemented with Spinal HDL☆155Updated last year
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆146Updated 2 years ago
- 这是使用FPGA开发CMOS的两个真实项目,之前的fpga_design仅是一个未完善的版本,同时也删除了一些与项目无关的东西☆36Updated 8 years ago