RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.
☆13Jan 9, 2020Updated 6 years ago
Alternatives and similar repositories for FusionAccel
Users that are interested in FusionAccel are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆16Jan 3, 2022Updated 4 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 8 years ago
- LSTM neural network (verilog)☆16Dec 5, 2018Updated 7 years ago
- Codes for our paper "Exploring Bit-Slice Sparsity in Deep Neural Networks for Efficient ReRAM-Based Deployment" [NeurIPS'19 EMC2 workshop]…☆10Oct 12, 2020Updated 6 years ago
- AFP is a hardware-friendly quantization framework for DNNs, which is contributed by Fangxin Liu and Wenbo Zhao.☆13Nov 8, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Systolic-array based Deep Learning Accelerator generator☆29Dec 11, 2020Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- HOG + SVM on FPGA☆28Dec 16, 2020Updated 5 years ago
- Digital Design Lab Spring 2019 Final Project☆13Jun 17, 2019Updated 7 years ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆13Mar 12, 2021Updated 5 years ago
- Fully Hardware-Based Stochastic Neural Network☆23Jan 23, 2025Updated last year
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 10 years ago
- Open Source Projects from Pallas Lab☆21Oct 10, 2021Updated 5 years ago
- ☆20Mar 21, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Open source AI ASIC chip for LLAMA inspired by Taalas☆17May 20, 2026Updated 5 months ago
- 基于RISC_V32I指令集架构的五级流水CPU☆15Sep 30, 2019Updated 7 years ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆16Aug 25, 2023Updated 3 years ago
- Convolution Neural Network of vgg19 model in verilog☆50Jan 4, 2018Updated 8 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆21Jul 9, 2024Updated 2 years ago
- An event based dataset loader under one common python API.☆10Mar 22, 2022Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Mar 25, 2019Updated 7 years ago
- Implementation of the paper : Not all attention is needed - Gated Attention Network for Sequence Data (GA-Net) [https://arxiv.org/abs/191…☆13Aug 20, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ILP SAT Detailed Router☆13Apr 14, 2020Updated 6 years ago
- A working AlphaZero implementation that's simple enough to be able to understand what's going on at a quick glance, without sacrificing t…☆14Mar 23, 2023Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆23Jun 1, 2021Updated 5 years ago
- Peking University Embedded Microprocessor System Lesson’s all Homework☆10Dec 28, 2021Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆36Jun 30, 2020Updated 6 years ago
- ☆24May 14, 2025Updated last year
- ☆73Dec 12, 2018Updated 7 years ago
- Using stereo vision 👀 to identify the obstacles by processing images on a FPGA☆25Feb 8, 2023Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆38Sep 25, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Mar 11, 2019Updated 7 years ago
- Camera model identification has earned paramount importance in the field of image forensics with an upsurge of digitally altered images w…☆14Jun 15, 2019Updated 7 years ago
- CNN on Artix-7 FPGA to perform pattern detection from a pool of objects☆12Sep 12, 2018Updated 8 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 7 years ago
- video prediction and world model research☆14Jun 10, 2022Updated 4 years ago
- Apple暑期返校送耳机活动监控，发现活动开始后通过邮件的方式提醒☆16Jun 16, 2020Updated 6 years ago