Springbone / CC-CamLinks
CC-Cam: A diffuser camera based on Pynq-Z2
☆19Updated 5 years ago
Alternatives and similar repositories for CC-Cam
Users that are interested in CC-Cam are comparing it to the libraries listed below
Sorting:
- Bilinear interpolation realizes image scaling based on FPGA☆28Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆24Updated 4 months ago
- use Verilog HDL implemente bicubic interpolation in FPGA☆26Updated 5 years ago
- 2019 SEU-Xilinx Summer School☆50Updated 6 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆63Updated 6 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Pynq computer vision examples with an OV5640 camera☆54Updated 5 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆52Updated 2 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- ☆94Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆136Updated last year
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆66Updated 3 years ago
- ☆18Updated 7 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆30Updated last year
- Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.☆35Updated 5 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- FIR implemention with Verilog☆48Updated 6 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆25Updated last year
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆40Updated 3 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆16Updated 5 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆52Updated 8 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆48Updated 6 years ago
- ☆24Updated 8 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- FFT generator using Chisel☆62Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆63Updated 5 years ago