Alternatives and similar repositories for vscode-riscv-venus:

Users that are interested in vscode-riscv-venus are comparing it to the libraries listed below

• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆205Updated this week
• Mariotti94 / WebRISC-V
  WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
  ☆135Updated last year
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆258Updated last month
• SpinalHDL / NaxRiscv
  ☆275Updated last week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆170Updated this week
• riscv-software-src / riscof
  ☆71Updated 4 months ago
• riscv-non-isa / riscv-arch-test
  ☆537Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆243Updated 3 months ago
• sifive / freedom-tools
  Tools for SiFive's Freedom Platform
  ☆215Updated 3 years ago
• kvakil / venus
  RISC-V instruction set simulator built for education
  ☆194Updated 2 years ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆369Updated last month
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆143Updated this week
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆472Updated this week
• riscv / riscv-plic-spec
  PLIC Specification
  ☆139Updated last year
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 3 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆424Updated 2 weeks ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆142Updated 3 months ago
• embench / embench-iot
  The main Embench repository
  ☆266Updated 5 months ago
• riscvarchive / riscv-code-size-reduction
  ☆151Updated 11 months ago
• merledu / nucleusrv
  NucleusRV - A 32-bit 5 staged pipelined risc-v core.
  ☆63Updated 2 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆156Updated this week
• noteed / riscv-hello-asm
  Bare metal RISC-V assembly hello world
  ☆54Updated 3 years ago
• johnwinans / riscv-toolchain-install-guide
  How to download & install qemu a toolchain suitable for building and running freestanding RISC-V C/C++ programs
  ☆53Updated 8 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆127Updated 3 weeks ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆152Updated 10 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆208Updated 10 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆101Updated 2 years ago
• ESEO-Tech / emulsiV
  A visual simulator for teaching computer architecture using the RISC-V instruction set
  ☆178Updated last year
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆108Updated 6 years ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆310Updated this week