Alternatives and similar repositories for riscv-from-scratch

Users that are interested in riscv-from-scratch are comparing it to the libraries listed below

• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆268Updated this week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 7 months ago
• noteed / riscv-hello-asm
  Bare metal RISC-V assembly hello world
  ☆57Updated 3 years ago
• riscvarchive / riscv-code-size-reduction
  ☆150Updated last year
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated last week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆182Updated 2 weeks ago
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆120Updated 2 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆98Updated 3 years ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆140Updated 2 years ago
• riscv-software-src / riscof
  ☆80Updated 2 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆143Updated last week
• franzflasch / riscv_em
  Simple risc-v emulator, able to run linux, written in C.
  ☆142Updated last year
• michaeljclark / busybear-linux
  busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.
  ☆98Updated 10 months ago
• s094392 / riscv-bare-metal
  A RISC-V bare metal example
  ☆47Updated 3 years ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆51Updated 4 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆237Updated 6 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆214Updated last week
• five-embeddev / riscv-scratchpad
  RISC-V Scratchpad
  ☆66Updated 2 years ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• riscv / riscv-aia
  ☆89Updated 2 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 2 months ago
• merledu / nucleusrv
  NucleusRV - A 32-bit 5 staged pipelined risc-v core.
  ☆66Updated last month
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆76Updated 3 weeks ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆38Updated 7 months ago
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆114Updated last year
• johnwinans / rvddt
  RISC-V Dynamic Debugging Tool
  ☆46Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 2 weeks ago
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆42Updated 10 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆117Updated 3 weeks ago