Alternatives and similar repositories for riscv-from-scratch

Users that are interested in riscv-from-scratch are comparing it to the libraries listed below

• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆51Updated 4 years ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆281Updated this week
• michaeljclark / busybear-linux
  busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.
  ☆98Updated last year
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆127Updated 2 years ago
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆116Updated 2 years ago
• five-embeddev / riscv-scratchpad
  RISC-V Scratchpad
  ☆70Updated 3 years ago
• noteed / riscv-hello-asm
  Bare metal RISC-V assembly hello world
  ☆63Updated 4 years ago
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆202Updated last year
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated this week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆198Updated 2 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆152Updated 6 months ago
• franzflasch / riscv_em
  Simple risc-v emulator, able to run linux, written in C.
  ☆144Updated last year
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆78Updated this week
• s094392 / riscv-bare-metal
  A RISC-V bare metal example
  ☆52Updated 3 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆151Updated last year
• riscv / riscv-aia
  ☆98Updated 3 months ago
• openhwgroup / corev-gcc
  ☆26Updated last year
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆75Updated 2 weeks ago
• michaelengel / xv6-d1
  Port of MIT's xv6 OS to the Nezha RISC-V board with Allwinner D1 SoC
  ☆107Updated 3 years ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆150Updated 3 months ago
• racerxdl / riscv-online-asm
  RISC-V Online Assembler using Emscripten, Gnu Binutils
  ☆59Updated 2 years ago
• riscvarchive / riscv-newlib
  RISC-V port of newlib
  ☆101Updated 3 years ago
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆225Updated 4 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆91Updated last month
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆56Updated 2 years ago
• riscvarchive / riscv-CMOs
  ☆89Updated 3 months ago
• embench / embench-iot
  The main Embench repository
  ☆297Updated last year
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆150Updated 3 years ago