Alternatives and similar repositories for ac_dsp

Users that are interested in ac_dsp are comparing it to the libraries listed below

• hlslibs / ac_math
  Algorithmic C Math Library
  ☆62Updated 5 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆52Updated 5 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆56Updated 2 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆65Updated 3 months ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆34Updated 7 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆38Updated 8 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆10Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated last year
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆32Updated 3 months ago
• obilaniu / MVU
  Neural Network accelerator powered by MVUs and RISC-V.
  ☆13Updated 9 months ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆34Updated 4 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆63Updated 11 months ago
• pulp-platform / pulp-dsp
  ☆33Updated 2 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 4 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 7 months ago
• pulp-platform / ri5cy_gnu_toolchain
  ☆23Updated 2 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆47Updated 4 years ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆29Updated 4 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆23Updated 6 years ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆42Updated 3 years ago
• chipsalliance / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆39Updated 2 weeks ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 7 months ago
• Minres / HIFIVE1-VP
  A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS
  ☆12Updated last year
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago