Alternatives and similar repositories for lightning

Users that are interested in lightning are comparing it to the libraries listed below

• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆152Updated last year
• open-photonics / lightning-lts
  [Long Term Support] [SIGCOMM 2023] Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference
  ☆16Updated 10 months ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• fpgasystems / Coyote
  Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…
  ☆279Updated last week
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆86Updated 3 months ago
• NetFPGA / NetFPGA-PLUS
  ☆53Updated last year
• Xilinx / Get_Moving_With_Alveo
  For publishing the source for UG1352 "Get Moving with Alveo"
  ☆50Updated 5 years ago
• Xilinx / open-nic-shell
  AMD OpenNIC Shell includes the HDL source files
  ☆118Updated 7 months ago
• Xilinx / RecoNIC
  RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.
  ☆142Updated 4 months ago
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆129Updated 3 years ago
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆109Updated 5 years ago
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆200Updated 3 years ago
• RC4ML / Shuhai
  Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…
  ☆112Updated last month
• spcl / pspin
  PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing
  ☆103Updated 2 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 2 years ago
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆214Updated last year
• ucsdsysnet / Rosebud
  Framework for FPGA-accelerated Middlebox Development
  ☆45Updated 2 years ago
• Xilinx / open-nic
  AMD OpenNIC Project Overview
  ☆274Updated 2 years ago
• ECASLab / cynq
  PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.
  ☆26Updated last week
• RC4ML / FpgaNIC
  FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]
  ☆131Updated last year
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆54Updated last year
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆173Updated this week
• kachris / survey_HA_LLM
  A survey on Hardware Accelerated LLMs
  ☆59Updated 6 months ago
• Xilinx / xup_aie_training
  Hands-on experience programming AI Engines using Vitis Unified Software Platform
  ☆41Updated last year
• Xilinx / open-nic-driver
  AMD OpenNIC driver includes the Linux kernel driver
  ☆67Updated 7 months ago
• rockyco / pulseDetector
  LLM-Aided FPGA Design for Signal Processing Applications
  ☆27Updated 2 months ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆149Updated this week
• esnet / esnet-smartnic-hw
  ESnet SmartNIC hardware design repository.
  ☆54Updated last week
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆155Updated 2 years ago