projf / fpgatoolsLinks
Tools for FPGA development.
☆49Updated 6 months ago
Alternatives and similar repositories for fpgatools
Users that are interested in fpgatools are comparing it to the libraries listed below
Sorting:
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆83Updated 5 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- Miscellaneous ULX3S examples (advanced)☆82Updated 7 months ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆66Updated 2 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆93Updated 7 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆46Updated 5 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆29Updated 4 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 7 years ago
- Wishbone interconnect utilities☆44Updated last month
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- FPGA USB 1.1 Low-Speed Implementation☆35Updated 7 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆32Updated 5 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆92Updated 7 months ago
- This repository contains small example designs that can be used with the open source icestorm flow.☆155Updated 4 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆77Updated this week
- Featherweight RISC-V implementation☆53Updated 4 years ago
- A FPGA core for a simple SDRAM controller.☆122Updated 4 years ago
- Yosys Plugins☆22Updated 6 years ago
- Minimal DVI / HDMI Framebuffer☆84Updated 5 years ago
- Wishbone controlled I2C controllers☆57Updated last year
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Nitro USB FPGA core☆86Updated last year
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Updated last year
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆61Updated 5 years ago
- ☆139Updated 3 weeks ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆35Updated 2 years ago
- Source code to accompany https://timetoexplore.net☆64Updated 5 years ago