Design a cache by using Verilog
☆13Jan 12, 2017Updated 9 years ago
Alternatives and similar repositories for CS-Cache
Users that are interested in CS-Cache are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 6 years ago
- ☆31Aug 8, 2020Updated 6 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 7 years ago
- 帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目☆12May 15, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A Verilog implementation of a processor cache.☆40Dec 29, 2017Updated 8 years ago
- ☆19Jun 3, 2019Updated 7 years ago
- SDRAM controller for MIPSfpga+ system☆24Oct 30, 2020Updated 5 years ago
- NSCSCC 2020 - Yet Another MIPS Processor☆14Aug 7, 2021Updated 5 years ago
- Simple cache design implementation in verilog☆55Nov 20, 2023Updated 2 years ago
- ☆14Jun 30, 2019Updated 7 years ago
- This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…☆83Apr 15, 2025Updated last year
- Dual-core 16-bit RISC processor☆12Jul 21, 2024Updated 2 years ago
- HiPU200 open-source version is a DNN accelerator, using RISC-V instruction set and customized vector/matrix extension.☆10Jan 7, 2022Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- 龙芯杯2021个人赛决赛最终代码☆11Sep 1, 2021Updated 5 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 10 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆56Aug 14, 2024Updated 2 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆49Jun 13, 2023Updated 3 years ago
- Simple test of ARM NEON code. Performs a blit to the framebuffer.☆15Jul 23, 2013Updated 13 years ago
- Parameterized verification framework (PCells, DRC, LVS) for Superconducting and Quantum Electronics.☆19Oct 11, 2019Updated 7 years ago
- A convolution based 3x3 GaussianBlur implementation using ARM NEON assembly engine☆10Jan 20, 2019Updated 7 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆19Oct 6, 2024Updated 2 years ago
- Two Level Cache Controller implementation in Verilog HDL☆69Jul 9, 2020Updated 6 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Verilog CAN controller that is compatible to the SJA 1000.☆20Apr 17, 2021Updated 5 years ago
- ☆13Jun 4, 2020Updated 6 years ago
- A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.☆16Aug 7, 2022Updated 4 years ago
- ☆35Jul 9, 2025Updated last year
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆45Aug 10, 2022Updated 4 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- Tensor Processing Unit implementation in Verilog☆16Aug 12, 2026Updated 2 months ago
- 简单易用的微信小程序倒计时库☆15May 15, 2018Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- USB2.0 Device Controller IP Core☆21Aug 18, 2023Updated 3 years ago
- ☆11Jun 28, 2020Updated 6 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design☆16Aug 21, 2026Updated last month
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Mar 17, 2022Updated 4 years ago
- AXI4 BFM in Verilog☆37Dec 13, 2016Updated 9 years ago
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆19May 30, 2016Updated 10 years ago