esnet / esnet-smartnic-hwView external linksLinks
ESnet SmartNIC hardware design repository.
☆60Feb 4, 2026Updated last week
Alternatives and similar repositories for esnet-smartnic-hw
Users that are interested in esnet-smartnic-hw are comparing it to the libraries listed below
Sorting:
- ESnet general-purpose FPGA design library.☆14Updated this week
- FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]☆140Aug 17, 2023Updated 2 years ago
- Ideas for P4 Projects.☆14Sep 18, 2024Updated last year
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆160Mar 20, 2025Updated 10 months ago
- AMD OpenNIC Project Overview☆303Dec 20, 2022Updated 3 years ago
- FlowBlaze: Stateful Packet Processing in Hardware☆71Nov 16, 2022Updated 3 years ago
- Always wanted to write performant P4 based networking application in Go but don't know where to start? Then this is the place to get to. …☆18Feb 24, 2023Updated 2 years ago
- RARE for P4Lang bmv2 dataplane target☆30Feb 6, 2026Updated last week
- P4 simulator module☆19Feb 3, 2026Updated last week
- Alkali is a MLIR-based compiler infrastructure for SmartNICs. It allows developers to write target-independent programs, with the compile…☆26Sep 28, 2025Updated 4 months ago
- P4.org's Participation in Google Summer of Code☆25Updated this week
- Network Development Kit (NDK) for FPGA cards with example application☆87Updated this week
- Virtual I/O acceleration technologies for KVM☆15Sep 17, 2013Updated 12 years ago
- This repo contains instructions, benchmarks, and files for running user space networking in gem5 simulator.☆11Aug 1, 2024Updated last year
- AMD OpenNIC Shell includes the HDL source files☆138Jan 2, 2025Updated last year
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- Generating P4 Code for the Application Layer☆15Sep 27, 2023Updated 2 years ago
- ☆33Nov 24, 2025Updated 2 months ago
- A curated list of awesome smartnic tutorials, papers and projects.☆291Oct 27, 2025Updated 3 months ago
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆13Sep 9, 2022Updated 3 years ago
- An accelerator to which you can offload RE matching☆14Dec 22, 2024Updated last year
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated 11 months ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆55Oct 9, 2023Updated 2 years ago
- ☆15Apr 18, 2023Updated 2 years ago
- TIP OOPT - Transponder Abstraction Interface☆44Feb 7, 2023Updated 3 years ago
- P4 formalization using Ott and HOL4☆15Jan 17, 2026Updated 3 weeks ago
- Reducing P4 Language’s Voluminosity using Higher-Level Constructs☆15Oct 15, 2022Updated 3 years ago
- Rewrite XuanTieC910 with chisel3☆12Jul 1, 2022Updated 3 years ago
- rc3☆72Jan 8, 2026Updated last month
- ☆36Jan 9, 2026Updated last month
- Portable NIC Architecture☆60Feb 15, 2024Updated 2 years ago
- Table-Driven Interface (TDI) for a P4-programmable backend device.☆41Jan 27, 2025Updated last year
- Morpheus: Domain Specific Run Time Optimization for Software Data Planes -- Presented at ASPLOS22☆35Apr 11, 2024Updated last year
- ☆13Apr 8, 2021Updated 4 years ago
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆73Jan 3, 2025Updated last year
- A Programmable Hardware Architecture for Network Transport Logic☆36Oct 26, 2021Updated 4 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated 11 months ago
- Artifacts for the "BBQ: A Fast and Scalable Integer Priority Queue for Hardware Packet Scheduling" paper that appears in NSDI '24.☆21Apr 23, 2024Updated last year