efabless / openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
☆276Updated last month
Alternatives and similar repositories for openlane2:
Users that are interested in openlane2 are comparing it to the libraries listed below
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆312Updated last month
- Fully Open Source FASOC generators built on top of open-source EDA tools☆265Updated last week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆491Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆319Updated last month
- Qflow full end-to-end digital synthesis flow for ASIC designs☆204Updated 5 months ago
- https://caravel-user-project.readthedocs.io☆193Updated last month
- Fabric generator and CAD tools☆163Updated last month
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆175Updated this week
- ☆314Updated last year
- ☆110Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆309Updated this week
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆148Updated 9 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆246Updated last month
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆213Updated last week
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆394Updated this week
- CORE-V Family of RISC-V Cores☆246Updated last month
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆367Updated this week
- Common SystemVerilog components☆593Updated last week
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆166Updated 5 years ago
- FOSS Flow For FPGA☆378Updated 2 months ago
- VeeR EL2 Core☆268Updated last week
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆150Updated 4 months ago
- Course material for a basic-level circuit design course using Xschem and ngspice☆91Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆235Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆383Updated last week
- SystemVerilog synthesis tool☆182Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆604Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆268Updated 2 weeks ago
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆444Updated last week