Alternatives and similar repositories for openlane2

Users that are interested in openlane2 are comparing it to the libraries listed below

• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆295Updated this week
• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆363Updated last week
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆356Updated 8 months ago
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆222Updated 8 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆197Updated last week
• IHP-GmbH / IHP-Open-PDK
  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
  ☆620Updated last week
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆219Updated last year
• mattvenn / awesome-opensource-asic-resources
  ☆352Updated 2 years ago
• sscs-ose / sscs-ose-code-a-chip.github.io
  IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
  ☆192Updated last month
• efabless / OpenLane
  This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …
  ☆158Updated last year
• google / sky90fd-pdk
  ☆118Updated 2 years ago
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• StefanSchippers / xschem
  A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…
  ☆411Updated last week
• ncsu-eda / FreePDK3
  ☆178Updated 4 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆158Updated 3 weeks ago
• The-OpenROAD-Project / OpenROAD-flow-scripts
  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
  ☆505Updated this week
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆575Updated this week
• iic-jku / analog-circuit-design
  Course material for a basic hands-on analog circuit design course with IC emphasis
  ☆152Updated this week
• google / gf180mcu-pdk
  PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
  ☆430Updated 2 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆302Updated 8 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆296Updated 2 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆215Updated 7 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆269Updated last week
• efabless / chipignite-resources
  ☆84Updated 2 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆235Updated last month
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆145Updated 3 weeks ago
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆143Updated this week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆409Updated 9 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆345Updated this week
• bmurmann / EE628
  EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)
  ☆167Updated 2 months ago