corundum / verilog-ethernetLinks
Verilog Ethernet components for FPGA implementation
☆20Updated last year
Alternatives and similar repositories for verilog-ethernet
Users that are interested in verilog-ethernet are comparing it to the libraries listed below
Sorting:
- Verilog PCI express components☆22Updated last year
- Open source FPGA-based NIC and platform for in-network compute☆65Updated 7 months ago
- ☆67Updated 2 years ago
- Ethernet switch implementation written in Verilog☆49Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 5 years ago
- ☆25Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- Ethernet interface modules for Cocotb☆67Updated last year
- Ethernet 10GE MAC☆45Updated 10 years ago
- Implementation of the PCIe physical layer☆42Updated last month
- UART -> AXI Bridge☆61Updated 3 years ago
- ☆26Updated 4 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆72Updated last year
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆17Updated 5 years ago
- UART models for cocotb☆29Updated 2 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆79Updated last year
- ☆59Updated 4 years ago
- Verilog Ethernet Switch (layer 2)☆44Updated last year
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- ☆21Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- A simple DDR3 memory controller☆55Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- PCI Express controller model☆57Updated 2 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago