chmmn / riscv-uclinuxLinks
riscv uclinux
☆14Updated 5 years ago
Alternatives and similar repositories for riscv-uclinux
Users that are interested in riscv-uclinux are comparing it to the libraries listed below
Sorting:
- ☆43Updated 4 years ago
- ☆25Updated 3 years ago
- AGM bitstream utilities and decoded files from Supra☆43Updated last year
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Updated 8 months ago
- buildroot fork☆37Updated last week
- Yet another free 8051 FPGA core☆35Updated 6 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆61Updated 3 weeks ago
- riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)☆80Updated 3 years ago
- Documenting the Anlogic FPGA bit-stream format.☆88Updated 2 years ago
- ☆19Updated 6 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆28Updated last year
- A baremetal experiment of Allwinner D1, without FEL☆32Updated 2 years ago
- A RISC-V processor☆15Updated 6 years ago
- 16 bit RISC-V proof of concept☆24Updated 9 months ago
- Trivial RISC-V Linux binary bootloader☆50Updated 4 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.☆98Updated 11 months ago
- FPGA implementation of the 8051 Microcontroller (Verilog)☆48Updated 10 years ago
- ☆17Updated 7 years ago
- USB 1.1 Host and Function IP core☆23Updated 10 years ago
- GDB Server for interacting with RISC-V models, boards and FPGAs☆20Updated 5 years ago
- Xilinx Virtual Cable implementation for ESP32☆33Updated 3 years ago
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆25Updated 3 years ago
- Python script for controlling the debug-jtag port of riscv cores☆14Updated 4 years ago
- Easy setup of GoWin FPGA SDK on Linux. A single script (main_launcher) automates all the critical steps and quickly fires up the IDE.☆22Updated 5 years ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- SDIO Device Verilog Core☆22Updated 6 years ago
- turbo 8051☆29Updated 7 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago