chmmn / riscv-uclinuxLinks
riscv uclinux
☆14Updated 5 years ago
Alternatives and similar repositories for riscv-uclinux
Users that are interested in riscv-uclinux are comparing it to the libraries listed below
Sorting:
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Documenting the Anlogic FPGA bit-stream format.☆88Updated 2 years ago
- ☆19Updated 6 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- AGM bitstream utilities and decoded files from Supra☆43Updated last year
- buildroot fork☆37Updated 3 weeks ago
- ☆46Updated 3 years ago
- ☆43Updated 4 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆28Updated last year
- FPGA implementation of the 8051 Microcontroller (Verilog)☆49Updated 10 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆99Updated 2 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 6 months ago
- Xilinx Virtual Cable Server for Raspberry Pi☆115Updated 3 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- Trivial RISC-V Linux binary bootloader☆51Updated 4 years ago
- Use an MPSSE FTDI device as a JTAG interface in Quartus tools☆22Updated last year
- Minimal DVI / HDMI Framebuffer☆83Updated 4 years ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆25Updated 6 years ago
- ☆46Updated 3 years ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- Linux capable RISC-V SoC designed to be readable and useful.☆151Updated last month
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Yet another free 8051 FPGA core☆35Updated 6 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆61Updated last month
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆79Updated last year
- USB 1.1 Host and Function IP core☆23Updated 11 years ago
- busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.☆98Updated last year
- Xilinx Virtual Cable implementation for ESP32☆34Updated 3 years ago
- Nitro USB FPGA core☆87Updated last year