fusesoc / fusesoc.github.io

Related projects: ⓘ

• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆63Updated 2 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆42Updated last year
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆49Updated last year
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆78Updated 4 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆35Updated 6 years ago
• icebreaker-fpga / icebreaker-verilog-examples
  This repository contains small example designs that can be used with the open source icestorm flow.
  ☆136Updated 2 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆167Updated this week
• olofk / vidbo
  Virtual Development Board
  ☆57Updated 2 years ago
• chipsalliance / Cores-SweRV_fpga
  ☆39Updated 4 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆105Updated last month
• SymbiFlow / nextpnr
  nextpnr portable FPGA place and route tool
  ☆20Updated last month
• SymbiFlow / yosys
  SymbiFlow WIP changes for Yosys Open SYnthesis Suite
  ☆37Updated 6 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆33Updated 8 months ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 2 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆47Updated 3 weeks ago
• gatecat / TrellisBoard
  Ultimate ECP5 development board
  ☆101Updated 5 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆80Updated 6 years ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆82Updated 6 months ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆57Updated last month
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆119Updated 8 months ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆128Updated last year
• emard / ulx3s-misc
  Miscellaneous ULX3S examples (advanced)
  ☆74Updated 10 months ago
• knielsen / ice40_viewer
  ☆57Updated 11 months ago
• kost / fujprog
  FPGA ULX2/3 JTAG programmer
  ☆38Updated last year
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆133Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆45Updated 6 months ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆84Updated 4 years ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆162Updated 3 weeks ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆34Updated 2 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆71Updated last year