britovski / adderLinks
Adder in VHDL to test the digital flow using ghdl and GTKwave (front-end) and openlane (back-end). Translated from the original https://github.com/staydh/adder
☆11Updated 3 years ago
Alternatives and similar repositories for adder
Users that are interested in adder are comparing it to the libraries listed below
Sorting:
- Co-simulation and behavioural verification with VHDL, C/C++ and Python/m☆13Updated this week
- ☆33Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆22Updated 3 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- ☆16Updated 7 months ago
- Small footprint and configurable Inter-Chip communication cores☆59Updated 3 weeks ago
- Dual RISC-V DISC with integrated eFPGA☆16Updated 3 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- A current mode buck converter on the SKY130 PDK☆27Updated 4 years ago
- USB virtual model in C++ for Verilog☆31Updated 8 months ago
- ☆16Updated 3 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Updated 2 years ago
- Open Source AES☆31Updated last year
- Virtual development board for HDL design☆42Updated 2 years ago
- SAR ADC on tiny tapeout☆42Updated 4 months ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 6 months ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- Repository containing the DSP gateware cores☆13Updated this week
- Library of FPGA architectures☆21Updated 2 weeks ago
- LunaPnR is a place and router for integrated circuits☆47Updated 7 months ago
- Demo board for TT4 and beyond☆21Updated 3 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated this week
- ☆36Updated 2 years ago
- RISC-V System on Chip Builder☆12Updated 4 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆27Updated 4 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated 3 weeks ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- ☆14Updated last year