Alternatives and similar repositories for adder:

Users that are interested in adder are comparing it to the libraries listed below

• YosysHQ / padring
  A padring generator for ASICs
  ☆24Updated last year
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last week
• b224hisl / rioschip
  ☆33Updated 2 years ago
• andrewattwood / fuserisc
  Dual RISC-V DISC with integrated eFPGA
  ☆16Updated 3 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆42Updated this week
• dbhi / vboard
  Virtual development board for HDL design
  ☆40Updated last year
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆20Updated 3 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆17Updated 3 weeks ago
• umarcor / SIEAV
  Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
  ☆13Updated this week
• efabless / caravel-lite
  ☆15Updated 2 months ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆28Updated 3 months ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆31Updated 8 months ago
• julianfl0w / openStreamHDL
  VHDL Code for infrastructural blocks (designed for FPGA)
  ☆13Updated 2 years ago
• krabo0om / pauloBlaze
  A plain VHDL implementation of a small microprocessor fully compatible with the ISA of the well known PicoBlaze by Ken Chapman.
  ☆22Updated 3 years ago
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated last year
• TinyTapeout / tt-demo-pcb
  Demo board for TT4 and beyond
  ☆20Updated last week
• tongchen126 / fpga_pcie_ethernet
  ☆15Updated 2 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆20Updated 11 months ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆26Updated 3 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆25Updated 5 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆45Updated last month
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆39Updated last year
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆26Updated 10 months ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆10Updated 2 years ago