craigjb / fuse-zynqLinks
Generate Zynq configurations without using the vendor GUI
☆30Updated 2 years ago
Alternatives and similar repositories for fuse-zynq
Users that are interested in fuse-zynq are comparing it to the libraries listed below
Sorting:
- Experimental flows using nextpnr for Xilinx devices☆49Updated 3 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated last week
- ☆79Updated last week
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆88Updated 2 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆64Updated last week
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆53Updated 3 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆81Updated 3 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- assorted library of utility cores for amaranth HDL☆96Updated 11 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆93Updated 5 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆68Updated 2 weeks ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆56Updated this week
- Flip flop setup, hold & metastability explorer tool☆48Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆95Updated 5 years ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆107Updated last year
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆177Updated last year
- ☆61Updated 4 years ago
- LiteX development baseboards arround the SQRL Acorn.☆69Updated 5 months ago
- FuseSoC standard core library☆147Updated 3 months ago
- ☆39Updated 2 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆44Updated 4 years ago
- System on Chip toolkit for Amaranth HDL☆92Updated 11 months ago
- ☆23Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated last year
- Naive Educational RISC V processor☆88Updated last month
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆82Updated this week