craigjb / fuse-zynqLinks
Generate Zynq configurations without using the vendor GUI
☆30Updated 2 years ago
Alternatives and similar repositories for fuse-zynq
Users that are interested in fuse-zynq are comparing it to the libraries listed below
Sorting:
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated last week
- Experimental flows using nextpnr for Xilinx devices☆54Updated last month
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆52Updated last week
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆82Updated 2 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆91Updated 6 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆186Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated last month
- ☆22Updated 3 years ago
- ☆38Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆81Updated 3 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆21Updated 2 weeks ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆34Updated 10 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆100Updated this week
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆31Updated 3 years ago
- ☆33Updated 3 years ago
- Naive Educational RISC V processor☆93Updated 2 months ago
- ☆88Updated 2 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆112Updated last year
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆75Updated last week
- assorted library of utility cores for amaranth HDL☆99Updated last year
- Wishbone interconnect utilities☆44Updated last week
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆92Updated 7 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Updated 8 months ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- Demo SoC for SiliconCompiler.☆62Updated last week