craigjb / fuse-zynq

Related projects ⓘ

Alternatives and complementary repositories for fuse-zynq

• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆39Updated this week
• FPGA-Research-Manchester / byteman
  Bitstream relocation and manipulation tool.
  ☆40Updated last year
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆48Updated last week
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆23Updated last week
• openXC7 / xc7k325t-blinky-nextpnr
  ☆43Updated last year
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆81Updated 2 months ago
• sparrowgrine / prjtritium
  ☆22Updated 2 years ago
• mattvenn / gtkwave-python-filter-process
  ☆29Updated 3 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆47Updated 11 months ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆82Updated 6 years ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆14Updated 3 months ago
• aignacio / mpsoc_example
  ☆57Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆37Updated 5 months ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆71Updated 2 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆33Updated 2 years ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated last week
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆85Updated 4 years ago
• b224hisl / rioschip
  ☆33Updated last year
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆83Updated 8 months ago
• pieter3d / simview
  ☆76Updated 8 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆64Updated 2 months ago
• andylithia / Project-Yatsuhashi-Chip1
  ☆39Updated last year
• esynr3z / proto245
  🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)
  ☆33Updated 3 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆18Updated 3 months ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆31Updated 2 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated 11 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆47Updated this week
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆58Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆74Updated 2 years ago