Alternatives and similar repositories for fuse-zynq:

Users that are interested in fuse-zynq are comparing it to the libraries listed below

• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆85Updated 4 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆30Updated this week
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆41Updated last month
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆18Updated 5 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆49Updated 2 weeks ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• mattvenn / gtkwave-python-filter-process
  ☆32Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated 8 months ago
• sparrowgrine / prjtritium
  ☆22Updated 2 years ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆51Updated last month
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 2 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆50Updated last year
• openXC7 / xc7k325t-blinky-nextpnr
  ☆44Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆82Updated 4 months ago
• blackmesalabs / sump3
  sump3 logic analyzer
  ☆18Updated last month
• dbhi / vboard
  Virtual development board for HDL design
  ☆40Updated last year
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆86Updated 4 years ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated this week
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆72Updated 2 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆84Updated 6 years ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆15Updated this week
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆26Updated last year
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆43Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆32Updated this week
• openXC7 / demo-projects
  Demo projects for various Kintex FPGA boards
  ☆49Updated 8 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago