craigjb / fuse-zynqLinks
Generate Zynq configurations without using the vendor GUI
☆30Updated 2 years ago
Alternatives and similar repositories for fuse-zynq
Users that are interested in fuse-zynq are comparing it to the libraries listed below
Sorting:
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆108Updated 2 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆57Updated this week
- Experimental flows using nextpnr for Xilinx devices☆51Updated 5 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆92Updated 4 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆63Updated 2 months ago
- ☆34Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆96Updated 5 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated 2 weeks ago
- assorted library of utility cores for amaranth HDL☆97Updated last year
- Bitstream relocation and manipulation tool.☆48Updated 2 years ago
- ☆87Updated last month
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆79Updated 3 weeks ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆111Updated last year
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- Naive Educational RISC V processor☆91Updated last month
- LiteX development baseboards arround the SQRL Acorn.☆71Updated 7 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- Demo projects for various Kintex FPGA boards☆64Updated 5 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆183Updated last year
- ☆38Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆33Updated 8 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated this week
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- ☆60Updated 4 years ago
- Wishbone interconnect utilities☆43Updated 9 months ago
- ☆71Updated last year
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Docker Development Environment for SpinalHDL☆20Updated last year