craigjb / fuse-zynqLinks
Generate Zynq configurations without using the vendor GUI
☆30Updated 2 years ago
Alternatives and similar repositories for fuse-zynq
Users that are interested in fuse-zynq are comparing it to the libraries listed below
Sorting:
- Experimental flows using nextpnr for Xilinx devices☆49Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆98Updated last week
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆91Updated 5 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆52Updated 2 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆175Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated this week
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆88Updated last month
- Flip flop setup, hold & metastability explorer tool☆36Updated 2 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆63Updated 2 weeks ago
- assorted library of utility cores for amaranth HDL☆94Updated 10 months ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 5 years ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆107Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 6 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆49Updated last month
- Minimal DVI / HDMI Framebuffer☆83Updated 4 years ago
- Demo projects for various Kintex FPGA boards☆60Updated 2 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated this week
- LiteX development baseboards arround the SQRL Acorn.☆68Updated 4 months ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆97Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- ☆70Updated 11 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆66Updated this week
- ☆79Updated last year
- ☆39Updated 2 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs☆68Updated 3 years ago
- ☆33Updated 2 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago