Alternatives and similar repositories for LoongArchCPU

Users that are interested in LoongArchCPU are comparing it to the libraries listed below

• EricJin2002 / UCAS-CA-2022
  一个单发射五级静态流水CPU，采用龙芯32位精简版指令集，支持异常和中断处理，使用AXI总线接口，已集成TLB模块
  ☆16Updated 2 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆145Updated last year
• iFuProcessor / iFuCore
  ☆20Updated last year
• cebarobot / UCAS-Computer-Architecture-Lab
  计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集
  ☆18Updated 4 years ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆61Updated last year
• OSCPU / yosys-sta
  ☆86Updated this week
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆29Updated 4 years ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆41Updated 5 years ago
• OSCPU / ysyxSoC
  ☆89Updated last month
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆15Updated last year
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆86Updated 5 years ago
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• Yawei-Ding / ysyx_riscv64_cpu
  ☆70Updated 2 years ago
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆48Updated 3 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆186Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆53Updated 3 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆82Updated 2 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆44Updated 5 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆32Updated 3 years ago
• USTC-System-Courses / CECS-Lab
  ☆40Updated 2 years ago
• TheRainstorm / PiplineMIPS
  A 5-level pipelined MIPS CPU with branch prediction and great cache.
  ☆20Updated 4 years ago
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆16Updated 6 years ago
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆24Updated last year
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆30Updated last year
• yizishun / ysyx-framework
  A framework for ysyx flow
  ☆12Updated last year
• loongson-community / open-la500
  Mirror of https://gitee.com/loongson-edu/open-la500.git
  ☆18Updated 10 months ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆25Updated 5 months ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆40Updated 2 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated last month