Verilog parsing and generator crate.
☆21Apr 16, 2020Updated 5 years ago
Alternatives and similar repositories for rust-verilog
Users that are interested in rust-verilog are comparing it to the libraries listed below
Sorting:
- My personal NixOS configs☆13Feb 26, 2026Updated last week
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 3 years ago
- Handle Fast Signal Traces (fst) in Python☆14Jun 11, 2025Updated 8 months ago
- P4FPGA is located at github.com/hanw/p4fpga☆13Jan 27, 2017Updated 9 years ago
- A simple library to use Rust's type system to handle endianness.☆18Jan 30, 2026Updated last month
- A fresh look at embedded Rust development☆35May 5, 2021Updated 4 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- Verilog generation tool written in Rust☆62Jun 29, 2023Updated 2 years ago
- Cross platform Instant Outbidding Bot, Instant Outbidder Bot is designed to outbid all real-time bids within a second by percentage incre…☆100Jan 17, 2023Updated 3 years ago
- A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COrouti…☆21Dec 24, 2023Updated 2 years ago
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- ☆24Feb 15, 2013Updated 13 years ago
- Implements embedded-hal traits by bitbanging☆50Aug 18, 2024Updated last year
- A verilog parser☆19Apr 12, 2024Updated last year
- Low level API definition of a Mutex☆26Jul 29, 2025Updated 7 months ago
- Easy cross-compilation of compiler-rt for bare metal ARM targets☆22Sep 11, 2016Updated 9 years ago
- A nicer HDL.☆98Apr 8, 2017Updated 8 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- ☆11May 31, 2016Updated 9 years ago
- A hardware compiler based on LLHD and CIRCT☆265Jun 30, 2025Updated 8 months ago
- Log file scanner used with EDA tools to classify errors and warnings☆12Nov 14, 2022Updated 3 years ago
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆32Jun 13, 2015Updated 10 years ago
- A standalone structural (gate-level) verilog parser☆40Feb 2, 2026Updated last month
- ☆30Jan 18, 2023Updated 3 years ago
- This is a SpyDrNet Plugin for a physical design related transformations☆16Jun 13, 2025Updated 8 months ago
- Experimental Nix implementation of Android `soong` modules☆10Oct 11, 2023Updated 2 years ago
- Sequence Planner☆12Nov 17, 2017Updated 8 years ago
- ERC-721 token that wraps a portion of ERC-20☆11Feb 21, 2019Updated 7 years ago
- Controlled Invariant Sets in Two Moves☆14Dec 21, 2021Updated 4 years ago
- Reading a SMA SunnyBoy solar inverter with an esp8266 or esp32☆11Feb 9, 2024Updated 2 years ago
- Translate a subset of C to Verilog☆12May 8, 2019Updated 6 years ago
- A tool for modeling FSMs by VHDL or Verilog☆11Updated this week
- sample VCD files☆43Feb 13, 2026Updated 3 weeks ago
- benchmarking e-graph extraction☆50Feb 2, 2026Updated last month
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- A copy of the latest version of MVSIS☆12Apr 18, 2021Updated 4 years ago
- Electro - easy commutation schematic editor written in Python + Qt (PyQt)☆14Mar 10, 2020Updated 5 years ago
- A linearizability checker for concurrent data structures☆12Aug 3, 2023Updated 2 years ago
- ☆10Jun 14, 2021Updated 4 years ago