Alternatives and similar repositories for rust-verilog

Users that are interested in rust-verilog are comparing it to the libraries listed below

• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• fabianschuiki / llhd-sim
  The LLHD reference simulator.
  ☆39Updated 4 years ago
• djg / verilated-rs
  Verilator Porcelain
  ☆47Updated last year
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆43Updated last year
• tcr / hoodlum
  A nicer HDL.
  ☆96Updated 8 years ago
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 5 years ago
• psurply / dwfv
  A simple digital waveform viewer with vi-like key bindings.
  ☆138Updated 4 months ago
• dalance / sdcx
  ☆13Updated last week
• yupferris / kaze
  An HDL embedded in Rust.
  ☆199Updated last year
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆93Updated 2 years ago
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆76Updated this week
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆56Updated 5 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 7 years ago
• SmithsDigitalForge / rust-hdl
  ☆30Updated 2 years ago
• stephank / rvsim
  A RISC-V simulator implementing RV32G[C].
  ☆35Updated 2 years ago
• litex-hub / pythondata-cpu-rocket
  Python module containing verilog files for rocket cpu (for use with LiteX).
  ☆14Updated last month
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆261Updated 2 weeks ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆34Updated 3 years ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆47Updated 6 months ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• japaric / ultrascale-plus
  Rust on the Zynq UltraScale+ MPSoC
  ☆42Updated 6 years ago
• ekiwi / fst-reader
  Native Rust implementation of the FST waveform format from GTKWave.
  ☆13Updated this week
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆43Updated last week
• aeste / aemb
  Multi-threaded 32-bit embedded core family.
  ☆24Updated 13 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆84Updated last year
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 9 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• ethanuppal / marlin
  🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
  ☆49Updated last month
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆21Updated 2 years ago