Alternatives and similar repositories for Hog

Users that are interested in Hog are comparing it to the libraries listed below

• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆192Updated last week
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆191Updated 2 years ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆230Updated last month
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆70Updated 2 months ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆243Updated last year
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆128Updated 6 months ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆251Updated this week
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆413Updated last week
• themperek / cocotb-test
  Unit testing for cocotb
  ☆165Updated 2 weeks ago
• kevinpt / symbolator
  HDL symbol generator
  ☆198Updated 2 years ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆119Updated 2 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆160Updated 2 weeks ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 10 months ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆417Updated 2 weeks ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆80Updated 3 weeks ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆161Updated 3 years ago
• raysalemi / Python4RTLVerification
  ☆170Updated 3 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆64Updated last year
• yol / ethernet_mac
  Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
  ☆175Updated last year
• svunit / svunit
  ☆207Updated 9 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆77Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆238Updated 3 months ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆142Updated last year
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆171Updated 3 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆302Updated 2 months ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated last week
• ZipCPU / dblclockfft
  A configurable C++ generator of pipelined Verilog FFT cores
  ☆251Updated last year
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆42Updated 2 months ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 9 years ago