Alternatives and similar repositories for Hog

Users that are interested in Hog are comparing it to the libraries listed below

• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆128Updated 7 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆194Updated last month
• themperek / cocotb-test
  Unit testing for cocotb
  ☆165Updated last month
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆71Updated 3 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆80Updated this week
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆64Updated last year
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆229Updated last week
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆163Updated 3 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆164Updated last month
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆118Updated 3 months ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆192Updated 2 years ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆253Updated last week
• yol / ethernet_mac
  Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
  ☆176Updated last year
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆245Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆144Updated this week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆305Updated 3 months ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆447Updated this week
• raysalemi / Python4RTLVerification
  ☆174Updated 3 years ago
• HDLForBeginners / Examples
  ☆115Updated 2 years ago
• Xilinx-Wiki-Projects / ZCU102-Ethernet
  Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.
  ☆81Updated this week
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 9 years ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆73Updated this week
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆81Updated 3 weeks ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆160Updated 10 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 5 months ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆70Updated last month
• kevinpt / symbolator
  HDL symbol generator
  ☆200Updated 2 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆73Updated 3 weeks ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆85Updated 2 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆242Updated 4 months ago