Hog (HDL-on-git) is an open-source tool to manage FPGA projects on git
☆69Aug 6, 2026Updated this week
Alternatives and similar repositories for Hog
Users that are interested in Hog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open Logic FPGA Standard Library☆997Jul 31, 2026Updated last week
- ☆22Dec 27, 2024Updated last year
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 4 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Jan 13, 2025Updated last year
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆219Jul 27, 2026Updated 2 weeks ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆41Feb 24, 2025Updated last year
- ☆20Jun 16, 2026Updated last month
- FPGA code for NeTV2☆16Dec 3, 2018Updated 7 years ago
- Unified Coverage Interoperability Standard (UCIS)☆15Jul 21, 2026Updated 2 weeks ago
- FPGA based image processing pipeline using zedboard, able to accelerate openCV functions☆17Apr 29, 2020Updated 6 years ago
- nMigen support for Xilinx Zynq devices☆17Nov 5, 2022Updated 3 years ago
- Zest is a FMC mezzanine board with 8 ADC channels and 2 DACs☆11Nov 6, 2024Updated last year
- Smart camera with OV 7670 and Zynq☆52May 17, 2022Updated 4 years ago
- The repository with my simple Z-turn examples, to be used as templates for more serious project☆18Apr 20, 2026Updated 3 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- An open-source HDL register code generator fast enough to run in real time.☆91Jul 27, 2026Updated 2 weeks ago
- VUnit GitHub action☆19May 23, 2021Updated 5 years ago
- ☆19Jan 13, 2021Updated 5 years ago
- A min-sum LDPC decoder written in SystemVerilog (IEEE 1800-2012)☆12Jan 8, 2021Updated 5 years ago
- ☆14Jul 27, 2026Updated 2 weeks ago
- Parse hardware design information to generate project specific machine configuration☆19Jul 8, 2026Updated last month
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆70Jul 29, 2026Updated last week
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- IOC for Rockwell - Allen Bradley PLC. (ControlLogix 5000)☆12Apr 22, 2026Updated 3 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Python library to generate XTCE XML☆13Jul 5, 2026Updated last month
- ☆15Sep 13, 2024Updated last year
- An OpenEmbedded layer for GNSS-SDR☆16Jul 5, 2026Updated last month
- ECE 4551: Computer Architecture☆11Nov 25, 2019Updated 6 years ago
- ERASynth Documentation☆22Feb 27, 2020Updated 6 years ago
- End-to-End Open-Source I2C GPIO Expander☆45Jul 23, 2026Updated 2 weeks ago
- IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet☆11Jun 2, 2021Updated 5 years ago
- A small, lightweight web server☆15Jan 21, 2021Updated 5 years ago
- A flexible and scalable development platform for modern FPGA projects.☆47Jul 28, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A tool for coherent synchrotron radiation modeling☆12May 20, 2022Updated 4 years ago
- Quantum Open Software for Secure Transmissions☆22Jun 29, 2024Updated 2 years ago
- C64 core☆14Jul 25, 2026Updated 2 weeks ago
- Control and status register code generator toolchain☆205Jul 14, 2026Updated 3 weeks ago
- BLonD (Beam Longitudinal Dynamics)☆25Updated this week
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Dec 6, 2021Updated 4 years ago
- ☆15Jul 28, 2016Updated 10 years ago