Alternatives and similar repositories for stx_cookbook

Users that are interested in stx_cookbook are comparing it to the libraries listed below

• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆168Updated 7 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆113Updated last year
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆270Updated last year
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆151Updated 4 months ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆94Updated last week
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆89Updated last year
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆123Updated last month
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆183Updated 2 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆252Updated 5 months ago
• raysalemi / Python4RTLVerification
  ☆161Updated 2 years ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆168Updated 2 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆161Updated 3 weeks ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆137Updated 3 weeks ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆92Updated 4 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆74Updated 10 years ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆66Updated 9 months ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆105Updated 3 years ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆160Updated last month
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆102Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆64Updated 4 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆202Updated 8 months ago
• accellera-official / uvm-core
  ☆87Updated 10 months ago
• svunit / svunit
  ☆204Updated 4 months ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆136Updated last year
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆87Updated 6 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆214Updated last week
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆41Updated 4 years ago
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆44Updated 10 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago