Altera Advanced Synthesis Cookbook 11.0
☆114Apr 7, 2023Updated 3 years ago
Alternatives and similar repositories for stx_cookbook
Users that are interested in stx_cookbook are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Revision Control Labs and Materials☆26Jan 23, 2018Updated 8 years ago
- Virtio front-end and back-end bridge, implemented with FPGA.☆28Sep 16, 2020Updated 5 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated last month
- Code for new techniques of VLSI placement☆13Oct 11, 2013Updated 12 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆28Jul 11, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Vijos: Vijos Isn't Just an Operating System☆10May 31, 2020Updated 5 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,539Mar 31, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆657Apr 3, 2026Updated last week
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 3 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Quick'n'dirty FuseSoC+cocotb example☆19Nov 26, 2024Updated last year
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- DDR3 controller for nMigen (WIP)☆14Dec 25, 2023Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A 5$ Xilinx ZYNQ development board.☆28Jan 25, 2023Updated 3 years ago
- ☆14Jul 28, 2022Updated 3 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 6 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆98May 24, 2022Updated 3 years ago
- Network Development Kit (NDK) for FPGA cards with example application☆92Updated this week
- Home of the Advanced Interface Bus (AIB) specification.☆58Aug 30, 2022Updated 3 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago
- ☆19Oct 29, 2025Updated 5 months ago
- ☆176Sep 11, 2022Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- JESD204b modules in VHDL☆30Apr 18, 2019Updated 6 years ago
- A python parser for decoding arm aarch32 and aarch64 system registers☆27Mar 29, 2026Updated last week
- Convolutional Neural Net written for implementation on an FPGA☆21Jun 26, 2017Updated 8 years ago
- ☆18Aug 26, 2016Updated 9 years ago
- A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spad…☆54Apr 2, 2026Updated last week
- A simple UVM example with DPI☆45Aug 7, 2017Updated 8 years ago
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆602Jul 30, 2025Updated 8 months ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Jan 6, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆23Apr 25, 2025Updated 11 months ago
- FPGA based modular synth.☆19Jan 8, 2017Updated 9 years ago
- ☆21Apr 2, 2023Updated 3 years ago
- opensource NPU for LLM inference (this run gpt2)☆62Feb 16, 2026Updated last month
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆23Oct 24, 2023Updated 2 years ago
- SystemRDL 2.0 language compiler front-end☆275Mar 24, 2026Updated 2 weeks ago
- Verilog AXI stream components for FPGA implementation☆879Feb 27, 2025Updated last year