dqi / ed25519_fpga
Exploring the Ed25519 (FPGA) design space.
☆16Updated 7 years ago
Alternatives and similar repositories for ed25519_fpga
Users that are interested in ed25519_fpga are comparing it to the libraries listed below
Sorting:
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- XCrypto: a cryptographic ISE for RISC-V☆93Updated 2 years ago
- Verilog implementation of the SHA-512 hash function.☆38Updated last month
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆31Updated last year
- SCARV: a side-channel hardened RISC-V platform☆26Updated 2 years ago
- ☆17Updated 2 years ago
- ☆81Updated last year
- True Random Number Generator core implemented in Verilog.☆75Updated 4 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆55Updated 4 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆53Updated 2 weeks ago
- Verilog 2001 implementation of the ChaCha stream cipher.☆40Updated last month
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆17Updated this week
- Open Source AES☆31Updated last year
- SpinalHDL - Cryptography libraries☆54Updated 9 months ago
- Run Rocket Chip on VCU128☆30Updated 5 months ago
- FIPS 202 compliant SHA-3 core in Verilog☆19Updated 4 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Updated 4 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last week
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆35Updated 5 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆13Updated 5 months ago
- Caribou: Distributed Smart Storage built with FPGAs☆65Updated 6 years ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆23Updated 2 years ago
- BSC Development Workstation (BDW)☆28Updated 6 months ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆23Updated 7 years ago
- Source-Opened RISCV for Crypto☆16Updated 3 years ago
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆38Updated last month
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago