dqi / ed25519_fpga
Exploring the Ed25519 (FPGA) design space.
☆16Updated 7 years ago
Alternatives and similar repositories for ed25519_fpga:
Users that are interested in ed25519_fpga are comparing it to the libraries listed below
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- XCrypto: a cryptographic ISE for RISC-V☆92Updated 2 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆35Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- ☆18Updated 6 years ago
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆12Updated this week
- IP submodules, formatted for easier CI integration☆29Updated last year
- Python module containing verilog files for rocket cpu (for use with LiteX).☆13Updated 2 months ago
- Verilog implementation of the SHA-512 hash function.☆38Updated 3 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆12Updated 4 months ago
- True Random Number Generator core implemented in Verilog.☆75Updated 4 years ago
- ☆17Updated 2 years ago
- Source-Opened RISCV for Crypto☆15Updated 3 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆31Updated last year
- Caribou: Distributed Smart Storage built with FPGAs☆66Updated 6 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆49Updated 2 weeks ago
- Small footprint and configurable Inter-Chip communication cores☆57Updated last month
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆33Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- BSC Development Workstation (BDW)☆28Updated 5 months ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- ☆78Updated last year
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆26Updated last year
- Virtio front-end and back-end bridge, implemented with FPGA.☆28Updated 4 years ago
- [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension☆27Updated 8 months ago
- A Verilog Synthesis Regression Test☆37Updated last year
- BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard☆47Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago