dqi / ed25519_fpgaView external linksLinks
Exploring the Ed25519 (FPGA) design space.
☆18Nov 23, 2017Updated 8 years ago
Alternatives and similar repositories for ed25519_fpga
Users that are interested in ed25519_fpga are comparing it to the libraries listed below
Sorting:
- A Setup for creating a Public Key Infrastructure backed by a YubiHSM2☆15Sep 7, 2023Updated 2 years ago
- Elgamal's over Elliptic Curves☆20Dec 22, 2018Updated 7 years ago
- A naive verilog/systemverilog formatter☆21Mar 22, 2025Updated 10 months ago
- SQLAlchemy models and DDL and ERD generation from chop-dbhi/data-models style JSON endpoints.☆11May 22, 2023Updated 2 years ago
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 6 years ago
- Homebrew images for 5etools.☆17Updated this week
- A dynamical admission control for Kubernetes to differentiate Pod belonging to a StatefulSet☆11Jan 31, 2022Updated 4 years ago
- ☆11Mar 22, 2024Updated last year
- Real time replication from MySQL to Neo4J using binary logs☆11Nov 13, 2015Updated 10 years ago
- Bring Your Own FIDO2 Extensions!☆16May 13, 2025Updated 9 months ago
- VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.☆13Mar 24, 2017Updated 8 years ago
- Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)☆11Jul 29, 2020Updated 5 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆10Oct 3, 2017Updated 8 years ago
- Manufacture peripheral Library - MPLib, modified by CooCox in order to add to CoIDE(http://www.coocox.org)☆12Jul 24, 2014Updated 11 years ago
- Equity Market Reinvented☆10Jan 11, 2023Updated 3 years ago
- A Framework for building Distributed Consensus Protocols☆10Oct 13, 2017Updated 8 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- Typesafe SDK for Revolut Business API https://www.revolut.com/it/business☆14Dec 6, 2022Updated 3 years ago
- Winform application for sending and receiving APDU command/response☆10Mar 19, 2019Updated 6 years ago
- Leightweigt, flexible and easily configurable OAuth2/OICD forward authentication service for use with traefik and nginx.☆13Nov 12, 2025Updated 3 months ago
- The ZOT Bounded Model/Satisfiability Checker (previously hosted as zot.googlecode.com)☆10Jan 11, 2021Updated 5 years ago
- Grand unified collection of headers to access various hardware chips and components☆19Aug 19, 2015Updated 10 years ago
- Lisa is a tool for (a). An LTLf to DFA conversion, and (b) An LTLf synthesis tool. Lisa supports both explicit and symbolic state-space r…☆12Sep 27, 2021Updated 4 years ago
- ☆14Feb 3, 2025Updated last year
- Vuejs porting library from jquery.complexify.js☆12Aug 17, 2021Updated 4 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 9 years ago
- an ssh based multitenant git host☆12Jun 3, 2023Updated 2 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆10Feb 11, 2021Updated 5 years ago
- [AAAI 2026] AutoTool: Efficient Tool Selection for Large Language Model Agents☆28Dec 28, 2025Updated last month
- 🤖 A telegram bot to monitor Tsinghua web learning and push new updates to user in Telegram.☆12Jul 22, 2025Updated 6 months ago
- minisatip for GXAPI☆13Nov 30, 2021Updated 4 years ago
- Fast Bytecode Analysis☆15Jan 2, 2016Updated 10 years ago
- Relational Programming DSL in Scala. Yet another minikanren port!☆15Nov 11, 2016Updated 9 years ago
- A Scala DSL (API) designed for monitoring event streams, such as for example log files. Based on data parameterized automata and temporal…☆11Dec 21, 2020Updated 5 years ago
- QR code 2005 encoder in Emacs Lisp☆10Feb 7, 2016Updated 10 years ago
- A rule-based stream reasoning engine utilizing sliding windows☆10Jun 3, 2022Updated 3 years ago
- Repository of benchmarks for SYNTCOMP☆14Sep 16, 2025Updated 4 months ago
- Tree-automata-based run-time type constraints for miniKanren☆14Aug 3, 2023Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago