secworks / chachaLinks
Verilog 2001 implementation of the ChaCha stream cipher.
☆40Updated 2 months ago
Alternatives and similar repositories for chacha
Users that are interested in chacha are comparing it to the libraries listed below
Sorting:
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆56Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated 3 weeks ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆40Updated 9 years ago
- chipy hdl☆17Updated 7 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 8 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆108Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Open Processor Architecture☆26Updated 9 years ago
- RISC-V XBitmanip Extension☆26Updated 6 years ago
- ☆60Updated last year
- PicoRV☆44Updated 5 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 8 years ago
- Copyleftist's Standard Cell Library☆99Updated last year
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- OpenFPGA☆34Updated 7 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 2 years ago
- An Open Source configuration of the Arty platform☆129Updated last year
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆78Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Documenting Lattice's 28nm FPGA parts☆143Updated last year
- Mutation Cover with Yosys (MCY)☆84Updated 2 weeks ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Yet Another RISC-V Implementation☆94Updated 9 months ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago