Alternatives and similar repositories for chacha:

Users that are interested in chacha are comparing it to the libraries listed below

• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆54Updated 5 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 7 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆116Updated 8 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆35Updated 9 months ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆27Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated 2 weeks ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆39Updated 9 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆57Updated 7 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆102Updated 10 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆65Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 2 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆69Updated 5 years ago
• secworks / blake2s
  Verilog implementation of the 32-bit version of the Blake2 hash function
  ☆21Updated last year
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆86Updated 3 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• knielsen / ice40_viewer
  ☆58Updated last year
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆37Updated 7 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 6 years ago
• SymbiFlow / yosys
  SymbiFlow WIP changes for Yosys Open SYnthesis Suite
  ☆37Updated 10 months ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• westerndigitalcorporation / omnixtend
  An open standard Cache Coherent Fabric Interface repository
  ☆65Updated 5 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• whitequark / Yumewatari
  妖刀夢渡
  ☆59Updated 5 years ago
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆106Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆29Updated 4 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆74Updated last year