secworks / chachaLinks
Verilog 2001 implementation of the ChaCha stream cipher.
☆42Updated 4 months ago
Alternatives and similar repositories for chacha
Users that are interested in chacha are comparing it to the libraries listed below
Sorting:
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆56Updated 5 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- An open standard Cache Coherent Fabric Interface repository☆67Updated 5 years ago
- LatticeMico32 soft processor☆106Updated 10 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 8 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Small footprint and configurable Ethernet core☆255Updated last week
- XCrypto: a cryptographic ISE for RISC-V☆93Updated 2 years ago
- RISC-V XBitmanip Extension☆26Updated 6 years ago
- The original high performance and small footprint system-on-chip based on Migen™☆333Updated 2 weeks ago
- A tiny POWER Open ISA soft processor written in Chisel☆110Updated 2 years ago
- A collection of MyHDL cores and tools for complex digital circuit design☆86Updated 6 years ago
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated last month
- Documenting Lattice's 28nm FPGA parts☆144Updated last year
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆40Updated 9 years ago
- Yet Another RISC-V Implementation☆97Updated 11 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆81Updated 3 years ago
- A time-predictable processor for mixed-criticality systems☆59Updated 9 months ago
- Open FPGA tools☆259Updated 5 years ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆203Updated 4 years ago
- Open Processor Architecture☆26Updated 9 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- chipy hdl☆17Updated 7 years ago
- Copyleftist's Standard Cell Library☆99Updated last year
- An Open Source configuration of the Arty platform☆131Updated last year
- ☆64Updated 6 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago