Alternatives and similar repositories for FPGA-SFP-communication-with-Aurora

Users that are interested in FPGA-SFP-communication-with-Aurora are comparing it to the libraries listed below

• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆60Updated last month
• Xilinx / pcie-model
  PCI Express controller model
  ☆66Updated 2 years ago
• corundum / verilog-pcie
  Verilog PCI express components
  ☆23Updated 2 years ago
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆67Updated 8 years ago
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆40Updated 2 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• riscveval / Rocket-Chip
  ☆26Updated 8 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆66Updated last month
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆30Updated last year
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 7 months ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆54Updated 2 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• DUNE / pl-nvme
  ☆36Updated 5 years ago
• sangwoojun / bluespecpcie
  PCIe library for the Xilinx 7 series FPGAs in the Bluespec language
  ☆82Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 4 months ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆65Updated 4 months ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• fpgasystems / davos
  Distributed Accelerator OS
  ☆63Updated 3 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 9 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆30Updated last year
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆39Updated last year
• fpgadeveloper / ethernet-fmc-processorless
  Example designs for using Ethernet FMC without a processor (ie. state machine based)
  ☆31Updated 10 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆35Updated 9 months ago
• aignacio / mpsoc_example
  ☆61Updated 4 years ago