defparam / higan-verilog
This is a higan/Verilator co-simulation example/framework
☆49Updated 6 years ago
Alternatives and similar repositories for higan-verilog:
Users that are interested in higan-verilog are comparing it to the libraries listed below
- J-Core J2/J32 5 stage pipeline CPU core☆50Updated 4 years ago
- MR1 formally verified RISC-V CPU☆54Updated 6 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- The PS-FPGA project (top level)☆23Updated 3 years ago
- Implementation of a circular queue in hardware using verilog.☆16Updated 5 years ago
- IRSIM switch-level simulator for digital circuits☆32Updated 10 months ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- LatticeMico32 soft processor☆104Updated 10 years ago
- ☆20Updated 3 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆44Updated 3 months ago
- SoftCPU/SoC engine-V☆54Updated last year
- Open Processor Architecture☆26Updated 8 years ago
- Reusable Verilog 2005 components for FPGA designs☆40Updated 3 weeks ago
- Port of Amber ARM Core project to Marsohod2 platform☆12Updated 5 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- The Original Nintendo Gameboy in Verilog☆54Updated 10 years ago
- Enigma in FPGA☆29Updated 5 years ago
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆44Updated 2 months ago
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆16Updated 4 years ago
- GDB Server for interacting with RISC-V models, boards and FPGAs☆21Updated 5 years ago
- Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)☆36Updated 3 years ago
- Waveform Generator☆11Updated 2 years ago
- Yet Another VHDL tool☆31Updated 7 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- ☆15Updated last year
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆31Updated 8 years ago
- This is the client side library to access JTAG Server distributed with Quartus (jtagd/jtagserver.exe). The protocol is known as Advanced …☆19Updated 7 months ago
- A bit-serial CPU☆18Updated 5 years ago
- OpenGL-like graphics pipeline on a Xilinx FPGA☆32Updated 14 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago