povik / foldLinks
high abstraction synthesis
☆14Updated last year
Alternatives and similar repositories for fold
Users that are interested in fold are comparing it to the libraries listed below
Sorting:
- ABC: System for Sequential Logic Synthesis and Formal Verification☆31Updated last week
- A modern schematic entry and simulation program☆84Updated this week
- Experiments with Yosys cxxrtl backend☆50Updated last year
- PicoRV☆43Updated 5 years ago
- mantle library☆44Updated 3 years ago
- Ultimate ECP5 development board☆116Updated 6 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- System on Chip toolkit for Amaranth HDL☆100Updated 2 weeks ago
- Example of how to use UVM with Verilator☆34Updated 2 months ago
- Prefix tree adder space exploration library☆56Updated 2 weeks ago
- Mutation Cover with Yosys (MCY)☆91Updated last week
- OpenFPGA☆34Updated 7 years ago
- Top level CedarEDA integration package☆28Updated last year
- End-to-end synthesis and P&R toolchain☆94Updated 2 months ago
- This repository contain source code for ngspice and ghdl integration☆34Updated last year
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Updated last month
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- Documenting the Lattice ECP5 bit-stream format.☆58Updated 2 years ago
- Collection of test cases for Yosys☆17Updated 4 years ago
- CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys☆21Updated 5 years ago
- ☆38Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Updated last week
- A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …☆48Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated 3 weeks ago
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆29Updated 2 months ago
- WAL enables programmable waveform analysis.☆164Updated 3 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Updated last week
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆68Updated 9 months ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆49Updated last year