Alternatives and similar repositories for fold:

Users that are interested in fold are comparing it to the libraries listed below

• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆54Updated last year
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆43Updated 2 weeks ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆48Updated 3 months ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• FOSSEE / nghdl
  This repository contain source code for ngspice and ghdl integration
  ☆30Updated 3 months ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆40Updated last week
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆43Updated 3 months ago
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 7 years ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆11Updated 2 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated 2 weeks ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆21Updated 3 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• m-labs / nmigen-boards
  Board and connector definition files for nMigen
  ☆30Updated 4 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆88Updated 6 months ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• openXC7 / toolchain-nix
  Nix flake for openXC7
  ☆34Updated 3 weeks ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• m-labs / microscope
  Finding the bacteria in rotting FPGA designs.
  ☆13Updated 4 years ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆78Updated 4 months ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆76Updated 4 years ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆32Updated 3 weeks ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆81Updated 3 weeks ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆96Updated this week
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated last week