tharunchitipolu / sobel-edge-detectorLinks
Sobel is first order or gradient based edge operator for images and it is implemented using verilog.
☆14Updated 4 years ago
Alternatives and similar repositories for sobel-edge-detector
Users that are interested in sobel-edge-detector are comparing it to the libraries listed below
Sorting:
- Hardware implementation of HDR image producing algorithm☆16Updated 2 years ago
- 关于数字IC的笔试面试题☆10Updated 5 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆14Updated 6 years ago
- HW and SW based implementation of Canny Edge Detection Algorithm.☆12Updated 7 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆18Updated 5 years ago
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆11Updated last year
- Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators☆10Updated last year
- 数字IC验证案例（SV and UVM）☆26Updated 4 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆16Updated 7 years ago
- wifi☆11Updated 8 years ago
- Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional N…☆16Updated last year
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆57Updated 2 years ago
- Digital IC design and vlsi notes☆12Updated 5 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Updated 7 years ago
- Polar codes are error correction codes developed by Erdal Arikan which achieves channel capacity and its reduced complexity makes it more…☆17Updated 4 years ago
- Physical Downlink Shared Channel (PDSCH) in 5G New Radio.☆10Updated last year
- Controller module for RISC-V core CI/CD☆17Updated 2 months ago
- 使用FPGA制作机器人，并使用python建立上位机，FPGA机器人通过控制ESP8266通过WiFi进行无线通讯，来达到上位机控制FPGA机器人的目的☆23Updated 5 years ago
- UVM/systemverilog/verilog/python VIM IDE☆16Updated 11 years ago
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆25Updated 7 years ago
- A python project to automatically generate the UVM testbench document.☆20Updated last year
- DSP University Project - Matlab, Simulations, and Verilog Files☆11Updated 5 years ago
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆10Updated 7 months ago
- Learn UVM by small projects☆11Updated 3 years ago
- FIR implemention with Verilog☆48Updated 6 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆44Updated 8 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆55Updated 2 years ago
- 基于FPGA的数字调制系统 ：实现m序列作为信源，并通过按键来选择移位相加的初始值和步进值以及实现2ASK、2FSK、2PSK☆18Updated 4 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago