An open-source Verilog implementation of Serial Peripheral Interface protocol with simulation support for efficient data exchange.
☆15Dec 26, 2023Updated 2 years ago
Alternatives and similar repositories for SPI
Users that are interested in SPI are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆77Dec 7, 2020Updated 5 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆22Jul 7, 2024Updated last year
- A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)☆10Jan 18, 2021Updated 5 years ago
- This is a SPI Master Module Written in Verilog☆14Aug 9, 2018Updated 7 years ago
- FreeRTOS port to ATMega328P☆13Apr 17, 2019Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆18Jun 7, 2020Updated 5 years ago
- ☆10Oct 20, 2023Updated 2 years ago
- ☆12Jul 17, 2020Updated 5 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆20Dec 15, 2019Updated 6 years ago
- MLX90640 library functions☆12Jan 9, 2019Updated 7 years ago
- An implementation of Lz77 compression algorithm on FPGA using MaxCompiler programming tool.☆10Sep 4, 2015Updated 10 years ago
- Synthetic aperture focusing technique for optoacoustic mesoscopy and scanning acoustic microscopy.☆13Jul 24, 2024Updated last year
- ☆26May 31, 2021Updated 4 years ago
- BIOS replacement for PC/XT clone☆22Mar 23, 2026Updated 3 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Controllable SVG elements in Node-RED Dashboard via UI Template node.☆16Mar 15, 2024Updated 2 years ago
- 毛泽东选集☆22Apr 20, 2020Updated 6 years ago
- Huffman encoding core (Vivado HLS Project)☆12Oct 15, 2019Updated 6 years ago
- An automated HDC platform☆11Mar 16, 2026Updated last month
- Codes for the paper "Deep Neural Networks with Multi-Branch Architectures Are Less Non-Convex"☆21Jul 25, 2020Updated 5 years ago
- Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем☆22Mar 7, 2026Updated last month
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- 《CPU设计实战》学习记录及代码☆14Dec 30, 2023Updated 2 years ago
- MNASNET Tensorflow☆23Apr 11, 2019Updated 7 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- Integrating Event-based Dynamic Vision Sensors with Sparse Hyperdimensional Computing☆12Jul 9, 2020Updated 5 years ago
- A CircuitPython RPN Calculator☆12Jul 22, 2025Updated 8 months ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Jul 17, 2019Updated 6 years ago
- Infrared Small Target Detection using TopHat Transformation.☆20Nov 14, 2018Updated 7 years ago
- configurable cordic core in verilog☆54Jul 17, 2014Updated 11 years ago
- ☆11Nov 24, 2020Updated 5 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Aug 28, 2025Updated 7 months ago
- A matlab R2018b realisation on 'Infrared Moving Small-Target Detection Using Spatial-Temporal Local Difference Measure' by Du P, Hamdulla…☆15Sep 11, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- fpga跑sobel识别算法☆47Mar 15, 2021Updated 5 years ago
- Human activity recognition using hyperdimensional computing based on Kinect's skeleton data☆11Jun 5, 2017Updated 8 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆17Feb 16, 2024Updated 2 years ago
- HLS code for Network on Chip (NoC)☆22Sep 11, 2020Updated 5 years ago
- ☆10Apr 21, 2025Updated 11 months ago
- UCSD CSE 237D Spring '20 Course Project☆19Sep 4, 2023Updated 2 years ago
- Convert WIDER Face Dataset to Tensorflow's TFRecord format.☆28Jun 18, 2018Updated 7 years ago