ZAIN-ALI-02 / SPI
An open-source Verilog implementation of Serial Peripheral Interface protocol with simulation support for efficient data exchange.
☆13Updated last year
Alternatives and similar repositories for SPI:
Users that are interested in SPI are comparing it to the libraries listed below
- configurable cordic core in verilog☆49Updated 10 years ago
- High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC☆13Updated 8 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆31Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- SDRAM controller with AXI4 interface☆91Updated 5 years ago
- All digital PLL☆28Updated 7 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆61Updated 8 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆61Updated last year
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆17Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- EE 272B - VLSI Design Project☆11Updated 3 years ago
- Verilog SPI master and slave☆53Updated 9 years ago
- Simple single-port AXI memory interface☆41Updated 10 months ago
- ☆52Updated 6 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆43Updated 7 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆73Updated 2 years ago
- upgrade to e203 (a risc-v core)☆42Updated 4 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- ☆36Updated 9 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆53Updated 4 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆23Updated last year
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year