Jacajack / hdlLinks
A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding
☆21Updated 4 months ago
Alternatives and similar repositories for hdl
Users that are interested in hdl are comparing it to the libraries listed below
Sorting:
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆74Updated last week
- Rust Test Bench - write HDL tests in Rust.☆23Updated 2 years ago
- VHDL Language Support for VSCode☆67Updated 3 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆46Updated 9 months ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆47Updated 6 months ago
- Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.☆39Updated 11 months ago
- WAL enables programmable waveform analysis.☆155Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- System on Chip toolkit for Amaranth HDL☆92Updated 9 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆66Updated this week
- A SystemVerilog source file pickler.☆59Updated 8 months ago
- D3.js based wave (signal) visualizer☆63Updated last year
- Fixed point math library for SystemVerilog☆27Updated 8 months ago
- Read and write VCD (Value Change Dump) files in Rust☆43Updated last year
- SystemVerilog frontend for Yosys☆135Updated last week
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆48Updated this week
- A command-line tool for displaying vcd waveforms.☆59Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- Raptor end-to-end FPGA Compiler and GUI☆83Updated 7 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆44Updated 5 months ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago
- An innovative Verilog-A compiler☆159Updated 10 months ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆115Updated 9 months ago
- Simple parser for extracting VHDL documentation☆71Updated last year
- Generate address space documentation HTML from compiled SystemRDL input☆54Updated 3 weeks ago
- ☆79Updated last year
- An automatic clock gating utility☆50Updated 3 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- Control and status register code generator toolchain☆138Updated last month