Jacajack / hdlLinks
A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding
☆22Updated 8 months ago
Alternatives and similar repositories for hdl
Users that are interested in hdl are comparing it to the libraries listed below
Sorting:
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆97Updated 2 months ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆48Updated 10 months ago
- VHDL Language Support for VSCode☆69Updated 7 months ago
- Fixed point math library for SystemVerilog☆36Updated 11 months ago
- Read and write VCD (Value Change Dump) files in Rust☆44Updated last year
- An innovative Verilog-A compiler☆166Updated last year
- Rust Test Bench - write HDL tests in Rust.☆23Updated 2 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated last year
- A simple digital waveform viewer with vi-like key bindings.☆143Updated 8 months ago
- WAL enables programmable waveform analysis.☆160Updated 2 weeks ago
- This repository is for (pre-)release versions of the Revolution EDA.☆46Updated this week
- A SystemVerilog language server based on the Slang library.☆56Updated this week
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- A command-line tool for displaying vcd waveforms.☆64Updated last year
- Raptor end-to-end FPGA Compiler and GUI☆86Updated 10 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆108Updated 2 months ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆120Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆116Updated last year
- An automatic clock gating utility☆51Updated 6 months ago
- Package manager and build system for VHDL, Verilog, and SystemVerilog☆57Updated this week
- Fabric generator and CAD tools graphical frontend☆17Updated 3 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆79Updated 3 weeks ago
- Fabric generator and CAD tools.☆203Updated this week
- SystemVerilog frontend for Yosys☆168Updated this week
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- D3.js based wave (signal) visualizer☆64Updated 2 months ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Updated 3 months ago
- Web-based HDL diagramming tool☆81Updated 2 years ago
- Coriolis VLSI EDA Tool (LIP6)☆72Updated 3 weeks ago