Alternatives and similar repositories for Verugent

Users that are interested in Verugent are comparing it to the libraries listed below

• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆35Updated 4 years ago
• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆45Updated 4 years ago
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆105Updated 3 years ago
• nananapo / veryl-riscv-book
  Let's write RISC-V CPU in Veryl!
  ☆50Updated last month
• garasubo / erkos
  A prototype embedded operating system written in Rust
  ☆61Updated 3 years ago
• yupferris / kaze
  An HDL embedded in Rust.
  ☆199Updated last year
• msyksphinz-self / swimmer_rust
  RISC-V Simulator written in Rust
  ☆20Updated 5 years ago
• djg / verilated-rs
  Verilator Porcelain
  ☆47Updated last year
• ethanuppal / marlin
  🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
  ☆49Updated last month
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆31Updated last year
• SmithsDigitalForge / rust-hdl
  ☆30Updated 2 years ago
• dalance / sdcx
  ☆13Updated this week
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆53Updated 4 years ago
• ciniml / fpga_samples
  FPGA samples
  ☆23Updated 4 months ago
• fabianschuiki / llhd-sim
  The LLHD reference simulator.
  ☆39Updated 4 years ago
• VLSI-JP / VLSI-JP.github.io
  ☆24Updated 3 weeks ago
• lmt-swallow / rvvisor
  [WIP] A tiny RISC-V hypervisor software written in Rust
  ☆27Updated 4 years ago
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 5 years ago
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆43Updated last year
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆261Updated last week
• japaric / ultrascale-plus
  Rust on the Zynq UltraScale+ MPSoC
  ☆42Updated 6 years ago
• defermelowie / bare-metal-rust-on-riscv
  A Simple template for bare metal Rust on RISC-V
  ☆18Updated last year
• tomoyuki-nakabayashi / book
  The Embedded Rust Bookの和訳レポジトリです
  ☆30Updated 4 years ago
• i4kimura / chisel-minicpu
  ☆14Updated 5 years ago
• ekiwi / pynq
  PYNQ with Chisel and Rust
  ☆25Updated 7 years ago
• calyxir / calyx-riscv
  RISCV Core written in Calyx
  ☆16Updated 10 months ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆105Updated 5 months ago
• horie-t / homemade-riscv
  『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
  ☆13Updated 5 years ago
• psurply / dwfv
  A simple digital waveform viewer with vi-like key bindings.
  ☆138Updated 4 months ago
• vengineer-systemverilog / All-of-SystemVerilog
  みんなのSystemVerilog
  ☆19Updated 3 years ago