RuSys / Verugent
Verilog generation tool written in Rust
☆58Updated last year
Alternatives and similar repositories for Verugent:
Users that are interested in Verugent are comparing it to the libraries listed below
- Write RISC-V CPU in Veryl☆31Updated last month
- Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)☆35Updated 3 years ago
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆105Updated 3 years ago
- The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.☆45Updated 4 years ago
- Open source RISC-V IP core for FPGA/ASIC design☆30Updated 9 months ago
- 🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆42Updated last month
- Verilator Porcelain☆47Updated last year
- ☆14Updated 5 years ago
- RISC-V Simulator written in Rust☆20Updated 5 years ago
- Polyphony is Python based High-Level Synthesis compiler.☆104Updated 3 months ago
- [WIP] A tiny RISC-V hypervisor software written in Rust☆27Updated 4 years ago
- FPGA samples☆23Updated 2 months ago
- みんなのSystemVerilog☆19Updated 2 years ago
- 『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ☆13Updated 5 years ago
- Read and write VCD (Value Change Dump) files in Rust☆43Updated last year
- ☆17Updated 2 years ago
- The LLHD reference simulator.☆37Updated 4 years ago
- ☆22Updated 2 months ago
- SubRISC: Simple Instruction-Set Computer for IoT edge devices☆16Updated 6 years ago
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆52Updated 8 years ago
- ☆13Updated 2 weeks ago
- RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo☆13Updated 5 years ago
- ☆30Updated 2 years ago
- SystemVerilog language server client for Visual Studio Code☆20Updated 2 years ago
- Instruction set simulator for RISC-V☆53Updated 4 years ago
- SystemVerilog linter☆342Updated last month
- PYNQ with Chisel and Rust☆25Updated 7 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Updated last year
- A hardware compiler based on LLHD and CIRCT☆256Updated last year
- ☆229Updated 2 years ago