RuSys / VerugentLinks
Verilog generation tool written in Rust
☆59Updated 2 years ago
Alternatives and similar repositories for Verugent
Users that are interested in Verugent are comparing it to the libraries listed below
Sorting:
- Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)☆36Updated 4 years ago
- The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.☆47Updated 4 years ago
- Open source RISC-V IP core for FPGA/ASIC design☆31Updated last year
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆107Updated 3 years ago
- Let's write RISC-V CPU in Veryl!☆53Updated last week
- A prototype embedded operating system written in Rust☆61Updated 3 years ago
- [WIP] A tiny RISC-V hypervisor software written in Rust☆27Updated 4 years ago
- Verilator Porcelain☆49Updated last year
- RISC-V Simulator written in Rust☆20Updated 5 years ago
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆65Updated last month
- An HDL embedded in Rust.☆200Updated last year
- ☆14Updated 6 years ago
- ☆26Updated last week
- The Embedded Rust Bookの和訳レポジトリです☆30Updated 4 years ago
- Instruction set simulator for RISC-V☆53Updated 5 years ago
- 『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ☆13Updated 6 years ago
- Polyphony is Python based High-Level Synthesis compiler.