jeff830107 / Deep-Learning-Hardware-Accelerator
Paper Collection of Deep Learning Hardware Accelerator
☆16Updated 5 years ago
Alternatives and similar repositories for Deep-Learning-Hardware-Accelerator:
Users that are interested in Deep-Learning-Hardware-Accelerator are comparing it to the libraries listed below
- ☆63Updated 6 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- ☆107Updated 4 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 5 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆149Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆178Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆155Updated 5 years ago
- An LeNet RTL implement onto FPGA☆45Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆29Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- ☆65Updated 2 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆33Updated 5 years ago
- ☆70Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆50Updated 6 years ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆12Updated 6 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆63Updated 2 months ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- A DNN Accelerator implemented with RTL.☆63Updated 3 months ago
- FPGA/AES/LeNet/VGG16☆102Updated 6 years ago
- ☆71Updated 2 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 3 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- ☆45Updated 6 years ago