cs3410 / logisim-evolution

Related projects ⓘ

Alternatives and complementary repositories for logisim-evolution

• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆80Updated 11 months ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆59Updated last week
• Obijuan / j1a-icestudio
  SwapForth J1a processor for Icestudio
  ☆12Updated 4 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆40Updated 6 years ago
• freecores / mcs-4
  4004 CPU and MCS-4 family chips
  ☆37Updated 10 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆52Updated 5 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆40Updated 11 months ago
• cpantel / DVGHV
  Designing Video Game Hardware in Verilog
  ☆26Updated 4 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆61Updated 7 months ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆64Updated 2 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆62Updated this week
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆57Updated last year
• hamsternz / simple-riscv
  A simple three-stage RISC-V CPU
  ☆21Updated 3 years ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆26Updated this week
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆28Updated 3 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆81Updated 6 months ago
• Obijuan / Z80-FPGA
  Z80 CPU for OpenFPGAs, with Icestudio
  ☆75Updated 5 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• grself / CIS221_Text
  This is the text for my Cochise College CIS 221 Digital Logic class
  ☆15Updated 4 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 4 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆44Updated last week
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆47Updated 11 months ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆58Updated 5 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆84Updated 5 years ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆97Updated 5 months ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆102Updated 10 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated last week
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆41Updated 3 weeks ago