Alternatives and similar repositories for j1a-icestudio:

Users that are interested in j1a-icestudio are comparing it to the libraries listed below

• Obijuan / Academia-Jedi-Hw
  Colecciones para el tutorial Electrónica digital para Makers con FPGAs Libres
  ☆11Updated 6 years ago
• Obijuan / Z80-FPGA
  Z80 CPU for OpenFPGAs, with Icestudio
  ☆77Updated 7 months ago
• Obijuan / iceFactory
  A Javascript library for generating blocks for the ICEstudio FPGA development environment
  ☆10Updated 6 years ago
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆15Updated 2 years ago
• Obijuan / nand2tetris-icestudio
  The Nand2tetris course, using icestudio for building hardware on Opensource FPGAs from the begining
  ☆30Updated 7 months ago
• microCore-VHDL / microCore
  Hardware/Software Co-design environment of a processor core for deterministic real time systems
  ☆37Updated last year
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆35Updated last year
• Anding / N.I.G.E.-Machine
  A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…
  ☆27Updated last month
• Obijuan / simplez-fpga
  Verilog implementation of the educational "Simplez" processor
  ☆41Updated 6 months ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆20Updated 5 years ago
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated last year
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆28Updated 3 weeks ago
• dan-rodrigues / ics-adpcm
  Programmable multichannel ADPCM decoder for FPGA
  ☆23Updated 4 years ago
• ElEctric-EyE / verilog-6502
  This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL
  ☆20Updated 4 years ago
• lawrie / verilog_examples
  Example code in Verilog for the Blackice II FPGA
  ☆27Updated 5 years ago
• lawrie / blackicemxbook
  ☆25Updated 5 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆24Updated 4 years ago
• Obijuan / RISC-V-FPGA
  RISC-V CPU for OpenFPGAs, in Icestudio
  ☆89Updated 7 months ago
• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆26Updated 5 years ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆12Updated 6 years ago
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆29Updated 3 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆81Updated last year
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆20Updated 7 years ago
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆48Updated 3 years ago
• zuloloxi / mecrisp-ice
  http://mecrisp.sourceforge.net/ Mecrisp-Ice is an enhanced version of Swapforth and the J1a stack processor by James Bowman, featuring th…
  ☆28Updated 8 years ago
• CospanDesign / nysa
  FPGA Development toolset
  ☆20Updated 7 years ago
• igor-m / UPduino-Mecrisp-Ice-15kB
  Mecrisp-Ice Forth running on 16bit j1a processor (iCE40UP5k based UPduino board) with full 15kB of bram and 48bit Floating Point Library.
  ☆18Updated 6 years ago