pulp-platform / hero-sdkLinks
⛔ DEPRECATED ⛔ HERO Software Development Kit
☆20Updated 3 years ago
Alternatives and similar repositories for hero-sdk
Users that are interested in hero-sdk are comparing it to the libraries listed below
Sorting:
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆41Updated 9 months ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆48Updated 4 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- PCI Express controller model☆61Updated 2 years ago
- ☆88Updated 2 years ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆88Updated 5 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆83Updated 10 months ago
- RISC-V GPGPU☆34Updated 5 years ago
- ☆15Updated 4 years ago
- Xilinx Unisim Library in Verilog☆82Updated 5 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated 10 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- ☆49Updated 3 months ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆107Updated 2 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 5 months ago
- Algorithmic C Math Library☆65Updated 2 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated last week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- ☆24Updated 8 years ago
- DDR4 Simulation Project in System Verilog☆42Updated 10 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆37Updated 4 years ago