Alternatives and similar repositories for hero-sdk:

Users that are interested in hero-sdk are comparing it to the libraries listed below

• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆55Updated 4 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated this week
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 7 months ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆34Updated 2 weeks ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆65Updated 2 months ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• PrincetonUniversity / primesim
  A parallel and distributed simulator for thousand-core chips
  ☆24Updated 7 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆18Updated 10 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆101Updated last year
• janweinstock / or1kmvp
  An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
  ☆12Updated last month
• accellera-official / systemc-common-practices
  SystemC Common Practices (SCP)
  ☆27Updated 5 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆54Updated this week
• riscveval / Rocket-Chip
  ☆23Updated 7 years ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆32Updated this week
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆111Updated this week
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆47Updated last month
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 4 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 3 months ago
• opencomputeproject / ODSA-BoW
  Repo for all activity related to the ODSA Bunch of Wires Specification
  ☆24Updated last year
• StanfordVLSI / Genesis2
  A home for Genesis2 sources.
  ☆41Updated this week
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆76Updated 4 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆57Updated 4 years ago