pulp-platform / hero-sdk
⛔ DEPRECATED ⛔ HERO Software Development Kit
☆20Updated 3 years ago
Alternatives and similar repositories for hero-sdk:
Users that are interested in hero-sdk are comparing it to the libraries listed below
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆43Updated 3 years ago
- RISC-V GPGPU☆34Updated 4 years ago
- The specification for the FIRRTL language☆49Updated last week
- ☆132Updated 2 years ago
- Xilinx Unisim Library in Verilog☆72Updated 4 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated 11 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated 3 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆34Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated this week
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆86Updated last year
- FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD☆32Updated 3 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆29Updated last month
- An LLVM based mini-C to Verilog High-level Synthesis tool☆35Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- OmniXtend cache coherence protocol☆78Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆98Updated last year
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- C++17 implementation of an AST for Verilog code generation☆24Updated last year
- FPGA reference design for the the Swerv EH1 Core☆69Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- PCI Express controller model☆47Updated 2 years ago
- HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…☆21Updated 8 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆58Updated last year
- Advanced Debug Interface☆12Updated last year
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 5 months ago