riscvarchive / riscv-code-speed-optimization

Related projects ⓘ

Alternatives and complementary repositories for riscv-code-speed-optimization

• XUANTIE-RV / thead-extension-spec
  XuanTie vendor extension Instruction Set spec
  ☆30Updated 2 months ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆17Updated 2 weeks ago
• riscvarchive / riscv-lld
  RISC-V port of LLVM Linker
  ☆24Updated 6 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆55Updated last month
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆14Updated 4 months ago
• cnrv / floating-point-guide
  《关于浮点运算：作为程序员都应该了解什么？》
  ☆29Updated 6 years ago
• Jonathan2251 / lbt
  Develop toolchain based on llvm to for Cpu0 processor
  ☆46Updated 10 months ago
• sifive / riscv-vector-intrinsic-fuzzing
  A random fuzz generator for the RISC-V vector extension intrinsics
  ☆18Updated 2 weeks ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated 7 months ago
• riscvarchive / riscv-edk2-platforms
  Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
  ☆18Updated 2 years ago
• Lichtso / riscv-llvm-templates
  Code templates to get started experimenting with the RISC-V LLVM toolchain
  ☆13Updated 5 years ago
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆71Updated last month
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆17Updated 4 years ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆74Updated this week
• atrosinenko / memtest86-plus-riscv
  Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)
  ☆15Updated 4 years ago
• stnolting / neorv32-riscof
  ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆25Updated this week
• rvkrypto / rvkrypto-fips
  [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension
  ☆26Updated 3 months ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆26Updated last year
• rgwan / bapi-rv32i
  A extremely size-optimized RV32I soft processor for FPGA.
  ☆27Updated 6 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆16Updated this week
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆40Updated this week
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆25Updated 4 years ago
• ThalesGroup / RISC-V-IoT-Contest
  RISC-V Soft CPU Security Contest by Thales and Microchip Technology
  ☆11Updated 5 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆30Updated 10 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆39Updated last year
• plctlab / RISCV-Training
  Training Materials for RISC-V HW/SW, focusing on compilers, emulators, and virtual machines. provided by PLCT Lab.
  ☆33Updated 6 months ago
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆20Updated last year
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago