riscvarchive / riscv-code-speed-optimizationLinks
☆12Updated 4 years ago
Alternatives and similar repositories for riscv-code-speed-optimization
Users that are interested in riscv-code-speed-optimization are comparing it to the libraries listed below
Sorting:
- Port of EDK2 implementation of UEFI to RISC-V. See documentation at:☆18Updated 3 years ago
- Develop toolchain based on llvm to for Cpu0 processor☆46Updated last month
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆21Updated 4 months ago
- 《关于浮点运算:作为程序员都应该了解什么?》☆28Updated 7 years ago
- CHERI-RISC-V model written in Sail☆60Updated 3 weeks ago
- Documentation of the RISC-V C API☆76Updated this week
- An instruction set simulator based on DBT-RISE implementing the RISC-V ISA☆35Updated 2 months ago
- OSDT社区(HelloGCC、HelloLLVM)组织的活动中的报告☆47Updated 4 years ago
- RISC-V port of LLVM Linker☆24Updated 6 years ago
- RTL blocks compatible with the Rocket Chip Generator☆16Updated 3 months ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Baremetal softwares for TrivialMIPS platform☆11Updated 5 years ago
- RISC-V Frontend Server☆63Updated 6 years ago
- XuanTie vendor extension Instruction Set spec☆39Updated last month
- Example implementation of Arm's Architecture Specification Language (ASL)☆118Updated 5 years ago
- A low-level intermediate representation for hardware description languages☆28Updated 5 years ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Updated 2 years ago
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆80Updated 2 weeks ago
- ☆47Updated 2 months ago
- PLCT实验室 V8 for RISC-V 的主仓库。2020年完成部署。☆23Updated 4 years ago
- Code templates to get started experimenting with the RISC-V LLVM toolchain☆14Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- RISC-V Online Help☆33Updated 4 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- RISC-V Static Binary Translator☆18Updated 6 years ago
- RISC-V backports for binutils-gdb. Development is done upstream at the FSF.☆149Updated 3 years ago
- RISC-V BSV Specification☆20Updated 5 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆37Updated 4 months ago
- Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)☆16Updated 5 years ago