hCODE-FPGA / hCODELinks
☆23Updated 6 years ago
Alternatives and similar repositories for hCODE
Users that are interested in hCODE are comparing it to the libraries listed below
Sorting:
- A port of FreeRTOS for the RISC-V ISA☆79Updated 6 years ago
- Light-weight RISC-V RV32IMC microcontroller core.☆104Updated 8 years ago
- ☆168Updated 4 years ago
- ☆110Updated 7 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- OpenRISC 1200 implementation☆176Updated 10 years ago
- OmniXtend cache coherence protocol☆82Updated 6 months ago
- Hardware design with Chisel☆35Updated 2 years ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago
- PCIe library for the Xilinx 7 series FPGAs in the Bluespec language☆82Updated 3 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- The OpenRISC 1000 architectural simulator☆77Updated 8 months ago
- Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.☆23Updated last month
- Connectal is a framework for software-driven hardware development.☆176Updated 2 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 7 months ago
- ☆46Updated 8 years ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆105Updated 7 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 6 years ago
- Porting OpenWrt to RISC-V - please check https://github.com/xfguo/riscv-openwrt-port for full instructions.☆54Updated 7 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- Ethernet switch implementation written in Verilog☆55Updated 2 years ago
- PulseRain Rattlesnake - RISCV RV32IMC Soft CPU☆34Updated 6 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- QEMU libsystemctlm-soc co-simulation demos.☆159Updated 7 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- ☆13Updated 4 years ago