hCODE-FPGA / hCODELinks
☆23Updated 7 years ago
Alternatives and similar repositories for hCODE
Users that are interested in hCODE are comparing it to the libraries listed below
Sorting:
- ☆110Updated 7 years ago
- A port of FreeRTOS for the RISC-V ISA☆79Updated 6 years ago
- ☆169Updated 4 years ago
- Hardware design with Chisel☆35Updated 3 years ago
- Connectal is a framework for software-driven hardware development.☆176Updated 2 years ago
- Porting OpenWrt to RISC-V - please check https://github.com/xfguo/riscv-openwrt-port for full instructions.☆54Updated 7 years ago
- OmniXtend cache coherence protocol☆82Updated 7 months ago
- Light-weight RISC-V RV32IMC microcontroller core.☆104Updated 8 years ago
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆42Updated last year
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- OpenRISC 1200 implementation☆178Updated 10 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆106Updated 7 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- PCIe library for the Xilinx 7 series FPGAs in the Bluespec language☆82Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated 2 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆60Updated 2 years ago
- ☆30Updated 10 months ago
- The OpenRISC 1000 architectural simulator☆77Updated 9 months ago
- Provides various testers for chisel users☆100Updated 3 years ago
- Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.☆23Updated 2 weeks ago
- Chisel Learning Journey☆111Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Updated 2 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆129Updated 8 months ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆73Updated last year
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc:de1…☆168Updated 2 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- EpicSim Project☆71Updated 4 years ago