Alternatives and similar repositories for hCODE

Users that are interested in hCODE are comparing it to the libraries listed below

• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆76Updated 6 years ago
• google / bottlerocket
  ☆109Updated 6 years ago
• Cosmos-OpenSSD / Cosmos-OpenSSD
  ☆43Updated 7 years ago
• xfguo / riscv-openwrt
  Porting OpenWrt to RISC-V - please check https://github.com/xfguo/riscv-openwrt-port for full instructions.
  ☆54Updated 6 years ago
• rgwan / kamikaze
  Light-weight RISC-V RV32IMC microcontroller core.
  ☆104Updated 8 years ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆76Updated 2 months ago
• fractalclone / zephyr-riscv
  Zephyr port to riscv architecture
  ☆24Updated 8 years ago
• lingscale / cc01
  ☆31Updated 4 months ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆54Updated 5 years ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆33Updated 2 years ago
• ilg-deprecated / riscv-none-gcc-build
  DEPRECATED! -> Project moved to xPack Dev Tools ->
  ☆6Updated 6 years ago
• LvNA-system / labeled-RISC-V
  ☆169Updated 4 years ago
• ucb-bar / midas-examples
  Simple MIDAS Examples
  ☆12Updated 6 years ago
• wzc810049078 / ZC-RISCV-CORE
  ZC RISCV CORE
  ☆13Updated 5 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆171Updated 9 years ago
• ilg-archived / riscv-none-gcc
  The GNU MCU Eclipse RISC-V Embedded GCC
  ☆79Updated 5 years ago
• aliyun / alibabacloud-fpga
  ☆20Updated 5 years ago
• PrincetonUniversity / piton-linux
  Linux Kernel for OpenPiton
  ☆35Updated 2 years ago
• ikwzm / FPGA-SoC-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc:de1…
  ☆163Updated 2 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Updated 3 years ago
• RISCV-on-Microsemi-FPGA / FreeRTOS
  FreeRTOS for RISC-V
  ☆26Updated 6 years ago
• FAST-Switch / fast
  FAST
  ☆39Updated 8 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆101Updated 6 years ago
• riscv-admin / riscv-ovpsim
  ☆62Updated 4 years ago
• cnrv / RISCV-East-Asia-Biweekly-Sync
  Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
  ☆23Updated last week