spr02 / DDSLinks
A DDS core written in VHDL.
☆11Updated 6 years ago
Alternatives and similar repositories for DDS
Users that are interested in DDS are comparing it to the libraries listed below
Sorting:
- SSD test project using Zynq Ultrascale+ bare metal NVMe.☆23Updated 4 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆125Updated 4 years ago
- Python productivity for RFSoC platforms☆85Updated last month
- PYNQ example of using the RFSoC as a QPSK transceiver.☆109Updated 2 years ago
- FPGA and Digital ASIC Build System☆80Updated last month
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆39Updated 10 months ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆45Updated 4 years ago
- VHDL-2008 Support Library☆57Updated 9 years ago
- RTL implementation of components for DVB-S2☆130Updated 2 years ago
- HDL code for a complex multiplier with AXI stream Interface☆13Updated 2 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆86Updated 2 years ago
- An RFSoC Frequency Planner developed using Python.☆31Updated 2 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆192Updated 2 weeks ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆71Updated 4 years ago
- QSPI flash support for Xilinx's Zynq devices☆25Updated 5 years ago
- A collection of phase locked loop (PLL) related projects☆115Updated last year
- RFSoC QSFP Data Offload Design with GNU Radio☆25Updated last year
- A testbench for an axi lite custom IP☆23Updated 11 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 3 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆88Updated last year
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆40Updated 2 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Updated 11 months ago
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated 7 months ago
- An open-source HDL register code generator fast enough to run in real time.☆78Updated last week
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 3 months ago
- HDL code for a DDS (direct digital synthesizer) with AXI stream interface☆23Updated 2 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆96Updated 5 years ago
- ☆33Updated 2 years ago
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago