Alternatives and similar repositories for KyogenRV

Users that are interested in KyogenRV are comparing it to the libraries listed below

• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆107Updated 3 years ago
• ryuz / jelly
  Original FPGA platform
  ☆69Updated this week
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆31Updated last year
• chadyuu / riscv-chisel-book
  ☆237Updated 2 years ago
• sakura-internet / nvme-pcie-to-fabrics-proxy
  (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…
  ☆25Updated 2 years ago
• ciniml / fpga_samples
  FPGA samples
  ☆23Updated last week
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆107Updated 8 months ago
• diningyo / dirv
  This is my first trial project for designing RISC-V in Chisel
  ☆17Updated last year
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 5 years ago
• vengineer-systemverilog / All-of-SystemVerilog
  みんなのSystemVerilog
  ☆19Updated 3 years ago
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆53Updated 5 years ago
• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆36Updated 4 years ago
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆163Updated last month
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 5 years ago
• RuSys / Verugent
  Verilog generation tool written in Rust
  ☆59Updated 2 years ago
• nananapo / veryl-riscv-book
  Let's write RISC-V CPU in Veryl!
  ☆54Updated 2 weeks ago
• i4kimura / chisel-minicpu
  ☆14Updated 6 years ago
• onikiri / onikiri2
  ☆39Updated last year
• horie-t / homemade-riscv
  『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
  ☆13Updated 6 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆44Updated last month
• ep2k / epGB
  Game Boy / Game Boy Color emulator running on an FPGA
  ☆18Updated last year
• shioyadan / meno
  Meno is a tool that visualizes hierarchical data, such as the sizes of directory trees or synthesized circuit sizes. It can be built into…
  ☆15Updated 2 months ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆39Updated 8 months ago
• MakeLSI / OpenRule1um
  Open design rule (1um)
  ☆21Updated 2 years ago
• aquaxis / FPGAMAG18
  FPGA Magazine No.18 - RISC-V
  ☆17Updated 8 years ago
• PyHDI / PyCoRAM
  Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
  ☆53Updated 8 years ago
• synthesijer / synthesijer
  ☆52Updated last year
• Hara-Laboratory / subrisc
  SubRISC: Simple Instruction-Set Computer for IoT edge devices
  ☆16Updated 7 years ago
• ciniml / seccamp_2022_riscv_cpu
  セキュリティキャンプ 2022 Y4 RISC-V CPU自作ゼミ 講義資料
  ☆29Updated last year
• moizumi99 / m99_riscv_emulator
  Simple RISC-V emulator
  ☆16Updated 5 years ago