Alternatives and similar repositories for lsfMonitor

Users that are interested in lsfMonitor are comparing it to the libraries listed below

• bytedance / ic_flow_platform
  IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …
  ☆185Updated 5 months ago
• xbwpc / EDA_FeatureColle
  A collection of license features from a varity of EDA vendors
  ☆79Updated 3 months ago
• liyanqing1987 / libView
  libView is a GUI tool for library file cell information view and comparison.
  ☆25Updated 2 years ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆77Updated 5 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆107Updated 2 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆92Updated 6 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆254Updated 9 months ago
• bytedance / batchRun
  batchRun is an ansible-similar IT automation system, which is more suitable for IC industry.
  ☆26Updated 3 months ago
• BinaryHackerLab / SynopsysMonoSlayer
  Synopsys License patcher
  ☆37Updated last year
• liyanqing1987 / libertyParser
  liberty parser (For parsing IC timing lib file)
  ☆65Updated 2 years ago
• zhuzhzh / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆25Updated 3 years ago
• cdsgit / cdsgit
  Cadence Virtuoso Git Integration written in SKILL++
  ☆158Updated 3 years ago
• ucb-art / BAG_framework
  ☆153Updated 2 years ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆54Updated 8 years ago
• ebecheto / Skill
  my cadence/virtuoso/icfb skill functions develloped over the years
  ☆144Updated last week
• advanced-uvm / second_edition
  Code for the second edition of Advanced UVM.
  ☆31Updated 8 years ago
• seabeam / yuu_register_productor
  UVM register utility generation by inputting xls table
  ☆39Updated 2 years ago
• zhajio1988 / my_vimrc
  Jude's vimrc for DV work(fine tuning for SV/UVM)
  ☆20Updated last year
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆144Updated 4 years ago
• mingzhang952 / uvm_auto
  uvm auto generator
  ☆24Updated 7 years ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆275Updated 2 years ago
• svunit / svunit
  ☆208Updated 8 months ago
• mperov / fixSegfaultVCS
  There is segmentation fault of VCS which should be fixed.
  ☆38Updated 2 years ago
• nachumk / systemverilog.vim
  SystemVerilog vim scripts
  ☆68Updated 2 years ago
• jmcneal / verilog-support
  Edit SystemVerilog files (and UVM files) in Vim/gVim
  ☆30Updated last year
• hjking / uvm_gen
  UVM Generator
  ☆47Updated last year
• zion-group / VerilogCodingStyle
  ☆65Updated 5 years ago
• accellera-official / uvm-core
  ☆100Updated last year
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆85Updated 4 years ago