liyanqing1987 / lsfMonitorLinks
A toop for LSF data-collection, data-analysis and information display.
☆57Updated last month
Alternatives and similar repositories for lsfMonitor
Users that are interested in lsfMonitor are comparing it to the libraries listed below
Sorting:
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆189Updated last week
- A collection of license features from a varity of EDA vendors☆84Updated 4 months ago
- libView is a GUI tool for library file cell information view and comparison.☆26Updated 2 years ago
- UVM 1.2 port to Python☆257Updated 10 months ago
- Synopsys License patcher☆38Updated last year
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆110Updated 2 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated last year
- batchRun is an ansible-similar IT automation system, which is more suitable for IC industry.☆27Updated 3 weeks ago
- Yet Another Simulation Architecture☆78Updated 5 years ago
- SystemVerilog vim scripts☆69Updated 2 years ago
- verilog filetype plugin to enable emacs verilog-mode autos☆25Updated 3 years ago
- Novel GUI Based UVM Testbench Template Builder☆147Updated 4 years ago
- ☆207Updated 9 months ago
- automatic-verilog based on vimscript☆280Updated 2 years ago
- There is segmentation fault of VCS which should be fixed.☆40Updated 2 years ago
- ☆104Updated last year
- Code for the second edition of Advanced UVM.☆31Updated 8 years ago
- Some useful documents of Synopsys☆93Updated 4 years ago
- [WIP] Dockerize Synopsys/Cadence EDA tools☆95Updated 6 years ago
- liberty parser (For parsing IC timing lib file)☆65Updated 2 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆153Updated 7 years ago
- ☆57Updated 9 years ago
- JSON lib in Systemverilog☆44Updated 3 years ago
- Edit SystemVerilog files (and UVM files) in Vim/gVim☆30Updated last year
- Cadence Virtuoso Git Integration written in SKILL++☆159Updated 3 years ago
- ☆158Updated 3 years ago
- Jude's vimrc for DV work(fine tuning for SV/UVM)☆20Updated last year
- A generic class library in SystemVerilog☆86Updated 4 years ago
- my cadence/virtuoso/icfb skill functions develloped over the years☆145Updated last month
- UVM register utility generation by inputting xls table☆39Updated 2 years ago