Alternatives and similar repositories for lsfMonitor

Users that are interested in lsfMonitor are comparing it to the libraries listed below

• bytedance / ic_flow_platform
  IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …
  ☆184Updated 4 months ago
• liyanqing1987 / libView
  libView is a GUI tool for library file cell information view and comparison.
  ☆25Updated 2 years ago
• xbwpc / EDA_FeatureColle
  A collection of license features from a varity of EDA vendors
  ☆75Updated last month
• BinaryHackerLab / SynopsysMonoSlayer
  Synopsys License patcher
  ☆36Updated last year
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆105Updated last year
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆76Updated 5 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆139Updated last year
• bytedance / batchRun
  batchRun is an ansible-similar IT automation system, which is more suitable for IC industry.
  ☆25Updated last month
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆144Updated 4 years ago
• zhajio1988 / my_vimrc
  Jude's vimrc for DV work(fine tuning for SV/UVM)
  ☆19Updated last year
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆91Updated 6 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆87Updated 3 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 8 months ago
• liyanqing1987 / libertyParser
  liberty parser (For parsing IC timing lib file)
  ☆65Updated 2 years ago
• seabeam / yuu_register_productor
  UVM register utility generation by inputting xls table
  ☆39Updated 2 years ago
• uvmdebug / uvm_debug
  UVM interactive debug library
  ☆35Updated 8 years ago
• hjking / uvm_gen
  UVM Generator
  ☆47Updated last year
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆51Updated 10 years ago
• jmcneal / verilog-support
  Edit SystemVerilog files (and UVM files) in Vim/gVim
  ☆30Updated last year
• zhuzhzh / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆25Updated 3 years ago
• advanced-uvm / second_edition
  Code for the second edition of Advanced UVM.
  ☆31Updated 8 years ago
• mperov / fixSegfaultVCS
  There is segmentation fault of VCS which should be fixed.
  ☆38Updated 2 years ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆54Updated 8 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆149Updated 7 years ago
• cdsgit / cdsgit
  Cadence Virtuoso Git Integration written in SKILL++
  ☆158Updated 3 years ago
• mingzhang952 / uvm_auto
  uvm auto generator
  ☆24Updated 7 years ago
• accellera / uvm
  ☆57Updated 9 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆56Updated 8 years ago
• accellera-official / uvm-core
  ☆98Updated last year
• The-OpenROAD-Project / asap7
  ☆194Updated 6 months ago